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-rw-r--r--include/llvm/Intrinsics.td23
1 files changed, 21 insertions, 2 deletions
diff --git a/include/llvm/Intrinsics.td b/include/llvm/Intrinsics.td
index a7fa1a97c4..119e77135b 100644
--- a/include/llvm/Intrinsics.td
+++ b/include/llvm/Intrinsics.td
@@ -626,7 +626,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
}
// SIMD load ops
-
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse_loadhps : GCCBuiltin<"__builtin_ia32_loadhps">,
Intrinsic<[llvm_v4f32_ty, llvm_ptr_ty], [IntrReadMem]>;
@@ -643,7 +642,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
}
// SIMD store ops
-
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse_storehps : GCCBuiltin<"__builtin_ia32_storehps">,
Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>;
@@ -659,6 +657,27 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>;
}
+// Cacheability support ops
+let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
+ def int_x86_sse_prefetch : GCCBuiltin<"__builtin_ia32_prefetch">,
+ Intrinsic<[llvm_ptr_ty, llvm_int_ty], [IntrWriteMem]>;
+}
+
+let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
+ def int_x86_sse_movntq : GCCBuiltin<"__builtin_ia32_movntq">,
+ Intrinsic<[llvm_ptr_ty, llvm_v2i32_ty], [IntrWriteMem]>;
+}
+
+let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
+ def int_x86_sse_movntps : GCCBuiltin<"__builtin_ia32_movntps">,
+ Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>;
+}
+
+let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
+ def int_x86_sse_sfence : GCCBuiltin<"__builtin_ia32_sfence">,
+ Intrinsic<[llvm_void_ty], [IntrWriteMem]>;
+}
+
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse_movmskps : GCCBuiltin<"__builtin_ia32_movmskps">,
Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [InstrNoMem]>;