diff options
| -rw-r--r-- | lib/Target/Skeleton/Skeleton.td | 40 | ||||
| -rw-r--r-- | lib/Target/Skeleton/SkeletonInstrInfo.td | 39 | ||||
| -rw-r--r-- | lib/Target/Skeleton/SkeletonRegisterInfo.td | 86 |
3 files changed, 165 insertions, 0 deletions
diff --git a/lib/Target/Skeleton/Skeleton.td b/lib/Target/Skeleton/Skeleton.td new file mode 100644 index 0000000000..2a5471ac16 --- /dev/null +++ b/lib/Target/Skeleton/Skeleton.td @@ -0,0 +1,40 @@ +//===- PowerPC.td - Describe the PowerPC Target Machine ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +// Get the target-independent interfaces which we are implementing... +// +include "../Target.td" + +//===----------------------------------------------------------------------===// +// Register File Description +//===----------------------------------------------------------------------===// + +include "SkeletonRegisterInfo.td" +include "SkeletonInstrInfo.td" + +def SkeletonInstrInfo : InstrInfo { + let PHIInst = PHI; +} + +def PowerPC : Target { + // Pointers are 32-bits in size. + let PointerType = i32; + + // Registers that must be saved by a function call go here. + let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19, + R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15, + F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, + F30, F31, CR2, CR3, CR4]; + + // Pull in Instruction Info: + let InstructionSet = SkeletonInstrInfo; +} diff --git a/lib/Target/Skeleton/SkeletonInstrInfo.td b/lib/Target/Skeleton/SkeletonInstrInfo.td new file mode 100644 index 0000000000..4df3614f24 --- /dev/null +++ b/lib/Target/Skeleton/SkeletonInstrInfo.td @@ -0,0 +1,39 @@ +//===- SkeletonInstrInfo.td - Describe the Instruction Set ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Skeleton instruction information. Fill in stuff here. +// +//===----------------------------------------------------------------------===// + +class Format<bits<4> val> { + bits<4> Value = val; +} + +// All of the PowerPC instruction formats, plus a pseudo-instruction format: +def Pseudo : Format<0>; +def IForm : Format<1>; +def BForm : Format<2>; + +// Look at how other targets factor commonality between instructions. +class SkelInst<string nm, bits<6> opcd, Format f> : Instruction { + let Namespace = "Skeleton"; + + let Name = nm; + bits<6> Opcode = opcd; + Format Form = f; + bits<4> FormBits = Form.Value; +} + +// Pseudo-instructions: +def PHI : SkelInst<"PHI", 0, Pseudo>; // PHI node... +def NOP : SkelInst<"NOP", 0, Pseudo>; // No-op +def ADJCALLSTACKDOWN : SkelInst<"ADJCALLSTACKDOWN", 0, Pseudo>; +def ADJCALLSTACKUP : SkelInst<"ADJCALLSTACKUP", 0, Pseudo>; + + diff --git a/lib/Target/Skeleton/SkeletonRegisterInfo.td b/lib/Target/Skeleton/SkeletonRegisterInfo.td new file mode 100644 index 0000000000..71c4aa21a4 --- /dev/null +++ b/lib/Target/Skeleton/SkeletonRegisterInfo.td @@ -0,0 +1,86 @@ +//===- SkeletonRegisterInfo.td - Describe the Register File -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the target's register file in Tablegen format. +// +//===----------------------------------------------------------------------===// + +class SkelReg : Register { + let Namespace = "Skeleton"; +} + +// This is roughly the PPC register file. You should replace all of this with +// whatever your target needs. + + +// GPR - One of the 32 32-bit general-purpose registers +class GPR<bits<5> num> : SkelReg { + field bits<5> Num = num; +} + +// SPR - One of the 32-bit special-purpose registers +class SPR<bits<5> num> : SkelReg { + field bits<5> Num = num; +} + +// FPR - One of the 32 64-bit floating-point registers +class FPR<bits<5> num> : SkelReg { + field bits<5> Num = num; +} + +// CR - One of the 8 4-bit condition registers +class CR<bits<5> num> : SkelReg { + field bits<5> Num = num; +} + +// General-purpose registers +def R0 : GPR< 0>; def R1 : GPR< 1>; def R2 : GPR< 2>; def R3 : GPR< 3>; +def R4 : GPR< 4>; def R5 : GPR< 5>; def R6 : GPR< 6>; def R7 : GPR< 7>; +def R8 : GPR< 8>; def R9 : GPR< 9>; def R10 : GPR<10>; def R11 : GPR<11>; +def R12 : GPR<12>; def R13 : GPR<13>; def R14 : GPR<14>; def R15 : GPR<15>; +def R16 : GPR<16>; def R17 : GPR<17>; def R18 : GPR<18>; def R19 : GPR<19>; +def R20 : GPR<20>; def R21 : GPR<21>; def R22 : GPR<22>; def R23 : GPR<23>; +def R24 : GPR<24>; def R25 : GPR<25>; def R26 : GPR<26>; def R27 : GPR<27>; +def R28 : GPR<28>; def R29 : GPR<29>; def R30 : GPR<30>; def R31 : GPR<31>; + +// Floating-point registers +def F0 : FPR< 0>; def F1 : FPR< 1>; def F2 : FPR< 2>; def F3 : FPR< 3>; +def F4 : FPR< 4>; def F5 : FPR< 5>; def F6 : FPR< 6>; def F7 : FPR< 7>; +def F8 : FPR< 8>; def F9 : FPR< 9>; def F10 : FPR<10>; def F11 : FPR<11>; +def F12 : FPR<12>; def F13 : FPR<13>; def F14 : FPR<14>; def F15 : FPR<15>; +def F16 : FPR<16>; def F17 : FPR<17>; def F18 : FPR<18>; def F19 : FPR<19>; +def F20 : FPR<20>; def F21 : FPR<21>; def F22 : FPR<22>; def F23 : FPR<23>; +def F24 : FPR<24>; def F25 : FPR<25>; def F26 : FPR<26>; def F27 : FPR<27>; +def F28 : FPR<28>; def F29 : FPR<29>; def F30 : FPR<30>; def F31 : FPR<31>; + +// Condition registers +def CR0 : CR<0>; def CR1 : CR<1>; def CR2 : CR<2>; def CR3 : CR<3>; +def CR4 : CR<4>; def CR5 : CR<5>; def CR6 : CR<6>; def CR7 : CR<7>; + +// Floating-point status and control register +def FPSCR : SPR<0>; +// fiXed-point Exception Register? :-) +def XER : SPR<1>; +// Link register +def LR : SPR<2>; +// Count register +def CTR : SPR<3>; +// These are the "time base" registers which are read-only in user mode. +def TBL : SPR<4>; +def TBU : SPR<5>; + +/// Register classes: one for floats and another for non-floats. +/// +def GPRC : RegisterClass<i32, 4, [R0, R1, R2, R3, R4, R5, R6, R7, + R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, + R22, R23, R24, R25, R26, R27, R28, R29, R30, R31]>; +def FPRC : RegisterClass<f64, 8, [F0, F1, F2, F3, F4, F5, F6, F7, + F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, + F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>; + |