aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--lib/Target/ARM/ARMInstrInfo.td16
-rw-r--r--lib/Target/ARM/ARMInstrThumb.td4
-rw-r--r--lib/Target/ARM/ARMInstrThumb2.td8
-rw-r--r--lib/Target/ARM/ARMInstrVFP.td16
4 files changed, 22 insertions, 22 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 6ff4bbb308..2eb6b04c5d 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1737,7 +1737,7 @@ def STRHT: AI3sthpo<(outs GPR:$base_wb),
multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
InstrItinClass itin, InstrItinClass itin_upd> {
- def IA :
+ def ia :
AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, f, itin,
!strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
@@ -1745,7 +1745,7 @@ multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
- def IA_UPD :
+ def ia_UPD :
AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, f, itin_upd,
!strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
@@ -1753,7 +1753,7 @@ multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
let Inst{21} = 1; // No writeback
let Inst{20} = L_bit;
}
- def DA :
+ def da :
AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, f, itin,
!strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
@@ -1761,7 +1761,7 @@ multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
- def DA_UPD :
+ def da_UPD :
AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, f, itin_upd,
!strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
@@ -1769,7 +1769,7 @@ multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
let Inst{21} = 1; // No writeback
let Inst{20} = L_bit;
}
- def DB :
+ def db :
AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, f, itin,
!strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
@@ -1777,7 +1777,7 @@ multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
- def DB_UPD :
+ def db_UPD :
AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, f, itin_upd,
!strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
@@ -1785,7 +1785,7 @@ multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
let Inst{21} = 1; // No writeback
let Inst{20} = L_bit;
}
- def IB :
+ def ib :
AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, f, itin,
!strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
@@ -1793,7 +1793,7 @@ multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
- def IB_UPD :
+ def ib_UPD :
AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, f, itin_upd,
!strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 73dfdc438a..54d3c16acc 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -539,11 +539,11 @@ def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
InstrItinClass itin_upd, bits<6> T1Enc,
bit L_bit> {
- def IA :
+ def ia :
T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin, !strconcat(asm, "${p}\t$Rn, $regs"), []>,
T1Encoding<T1Enc>;
- def IA_UPD :
+ def ia_UPD :
T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin_upd, !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
T1Encoding<T1Enc>;
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 7305e4950d..59313cd09c 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -1285,7 +1285,7 @@ defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
InstrItinClass itin_upd, bit L_bit> {
- def IA :
+ def ia :
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
bits<4> Rn;
@@ -1300,7 +1300,7 @@ multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
let Inst{19-16} = Rn;
let Inst{15-0} = regs;
}
- def IA_UPD :
+ def ia_UPD :
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
bits<4> Rn;
@@ -1315,7 +1315,7 @@ multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
let Inst{19-16} = Rn;
let Inst{15-0} = regs;
}
- def DB :
+ def db :
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
bits<4> Rn;
@@ -1330,7 +1330,7 @@ multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
let Inst{19-16} = Rn;
let Inst{15-0} = regs;
}
- def DB_UPD :
+ def db_UPD :
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
bits<4> Rn;
diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index 046bed66f1..72ff7239f9 100644
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -76,7 +76,7 @@ def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
multiclass vfp_ldst_d_mult<string asm, bit L_bit,
InstrItinClass itin, InstrItinClass itin_upd> {
- def IA :
+ def ia :
AXDI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, itin,
!strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
@@ -84,7 +84,7 @@ multiclass vfp_ldst_d_mult<string asm, bit L_bit,
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
- def IA_UPD :
+ def ia_UPD :
AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, itin_upd,
!strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
@@ -92,7 +92,7 @@ multiclass vfp_ldst_d_mult<string asm, bit L_bit,
let Inst{21} = 1; // Writeback
let Inst{20} = L_bit;
}
- def DB :
+ def db :
AXDI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, itin,
!strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
@@ -100,7 +100,7 @@ multiclass vfp_ldst_d_mult<string asm, bit L_bit,
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
- def DB_UPD :
+ def db_UPD :
AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, itin_upd,
!strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
@@ -112,7 +112,7 @@ multiclass vfp_ldst_d_mult<string asm, bit L_bit,
multiclass vfp_ldst_s_mult<string asm, bit L_bit,
InstrItinClass itin, InstrItinClass itin_upd> {
- def IA :
+ def ia :
AXSI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, itin,
!strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
@@ -120,7 +120,7 @@ multiclass vfp_ldst_s_mult<string asm, bit L_bit,
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
- def IA_UPD :
+ def ia_UPD :
AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, itin_upd,
!strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
@@ -128,7 +128,7 @@ multiclass vfp_ldst_s_mult<string asm, bit L_bit,
let Inst{21} = 1; // Writeback
let Inst{20} = L_bit;
}
- def DB :
+ def db :
AXSI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, itin,
!strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
@@ -136,7 +136,7 @@ multiclass vfp_ldst_s_mult<string asm, bit L_bit,
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
- def DB_UPD :
+ def db_UPD :
AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, itin_upd,
!strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-09-21 16:44:56 +0000