diff options
| -rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 3 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 3 | ||||
| -rw-r--r-- | lib/Target/ARM/NEONPreAllocPass.cpp | 3 |
3 files changed, 0 insertions, 9 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index a773916eb2..b2c6e12a0f 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -1317,7 +1317,6 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { case MVT::v4i16: Opc = ARM::VLD2d16; break; case MVT::v2f32: case MVT::v2i32: Opc = ARM::VLD2d32; break; - case MVT::v1i64: Opc = ARM::VLD2d64; break; } const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc }; return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 3); @@ -1335,7 +1334,6 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { case MVT::v4i16: Opc = ARM::VLD3d16; break; case MVT::v2f32: case MVT::v2i32: Opc = ARM::VLD3d32; break; - case MVT::v1i64: Opc = ARM::VLD3d64; break; } const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc }; return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 3); @@ -1353,7 +1351,6 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { case MVT::v4i16: Opc = ARM::VLD4d16; break; case MVT::v2f32: case MVT::v2i32: Opc = ARM::VLD4d32; break; - case MVT::v1i64: Opc = ARM::VLD4d64; break; } const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc }; std::vector<MVT> ResTys(4, VT); diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index d31ec416ea..45284b640f 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -196,7 +196,6 @@ class VLD2D<string OpcodeStr> def VLD2d8 : VLD2D<"vld2.8">; def VLD2d16 : VLD2D<"vld2.16">; def VLD2d32 : VLD2D<"vld2.32">; -def VLD2d64 : VLD2D<"vld2.64">; // VLD3 : Vector Load (multiple 3-element structures) class VLD3D<string OpcodeStr> @@ -206,7 +205,6 @@ class VLD3D<string OpcodeStr> def VLD3d8 : VLD3D<"vld3.8">; def VLD3d16 : VLD3D<"vld3.16">; def VLD3d32 : VLD3D<"vld3.32">; -def VLD3d64 : VLD3D<"vld3.64">; // VLD4 : Vector Load (multiple 4-element structures) class VLD4D<string OpcodeStr> @@ -217,7 +215,6 @@ class VLD4D<string OpcodeStr> def VLD4d8 : VLD4D<"vld4.8">; def VLD4d16 : VLD4D<"vld4.16">; def VLD4d32 : VLD4D<"vld4.32">; -def VLD4d64 : VLD4D<"vld4.64">; //===----------------------------------------------------------------------===// diff --git a/lib/Target/ARM/NEONPreAllocPass.cpp b/lib/Target/ARM/NEONPreAllocPass.cpp index 1662b76394..bf9a72bcd2 100644 --- a/lib/Target/ARM/NEONPreAllocPass.cpp +++ b/lib/Target/ARM/NEONPreAllocPass.cpp @@ -45,7 +45,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, case ARM::VLD2d8: case ARM::VLD2d16: case ARM::VLD2d32: - case ARM::VLD2d64: FirstOpnd = 0; NumRegs = 2; return true; @@ -53,7 +52,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, case ARM::VLD3d8: case ARM::VLD3d16: case ARM::VLD3d32: - case ARM::VLD3d64: FirstOpnd = 0; NumRegs = 3; return true; @@ -61,7 +59,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, case ARM::VLD4d8: case ARM::VLD4d16: case ARM::VLD4d32: - case ARM::VLD4d64: FirstOpnd = 0; NumRegs = 4; return true; |