diff options
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index a1b2b2ae72..5999b155ae 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -16967,29 +16967,30 @@ static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) { EVT VT = N->getValueType(0); - + if (!VT.isVector()) return SDValue(); SDValue In = N->getOperand(0); EVT InVT = In.getValueType(); DebugLoc dl = N->getDebugLoc(); - unsigned ExtenedEltSize = VT.getVectorElementType().getSizeInBits(); + unsigned ExtendedEltSize = VT.getVectorElementType().getSizeInBits(); // Split SIGN_EXTEND operation to use vmovsx instruction when possible if (InVT == MVT::v8i8) { - if (ExtenedEltSize > 16 && !Subtarget->hasInt256()) + if (ExtendedEltSize > 16 && !Subtarget->hasInt256()) In = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, In); - if (ExtenedEltSize > 32) + if (ExtendedEltSize > 32) In = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i32, In); return DAG.getNode(ISD::SIGN_EXTEND, dl, VT, In); } if ((InVT == MVT::v4i8 || InVT == MVT::v4i16) && - ExtenedEltSize > 32 && !Subtarget->hasInt256()) { + ExtendedEltSize > 32 && !Subtarget->hasInt256()) { In = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, In); return DAG.getNode(ISD::SIGN_EXTEND, dl, VT, In); } + if (!DCI.isBeforeLegalizeOps()) return SDValue(); |