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-rw-r--r--lib/Target/ARM/ARMConstantIslandPass.cpp3
-rw-r--r--lib/Target/ARM/ARMISelDAGToDAG.cpp25
-rw-r--r--lib/Target/ARM/ARMInstrThumb.td6
3 files changed, 25 insertions, 9 deletions
diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp
index 183bde8824..2b5227a160 100644
--- a/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -245,6 +245,9 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &Fn,
case ARMII::AddrModeT4:
MaxOffs = 1 << (5+2);
break;
+ case ARMII::AddrModeTs:
+ MaxOffs = 1 << (8+2);
+ break;
}
// Remember that this is a user of a CP entry.
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 9b06adda9c..4c6fce6efa 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -380,6 +380,9 @@ ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDOperand Op, SDOperand N,
SDOperand TmpBase, TmpOffImm;
if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
return false; // We want to select tLDRspi / tSTRspi instead.
+ if (N.getOpcode() == ARMISD::Wrapper &&
+ N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
+ return false; // We want to select tLDRpci instead.
}
if (N.getOpcode() != ISD::ADD) {
@@ -505,14 +508,20 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
SDOperand CPIdx =
CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
TLI.getPointerTy());
- SDOperand Ops[] = {
- CPIdx,
- CurDAG->getRegister(0, MVT::i32),
- CurDAG->getTargetConstant(0, MVT::i32),
- CurDAG->getEntryNode()
- };
- SDNode *ResNode =
- CurDAG->getTargetNode(ARM::LDR, MVT::i32, MVT::Other, Ops, 4);
+
+ SDNode *ResNode;
+ if (Subtarget->isThumb())
+ ResNode = CurDAG->getTargetNode(ARM::tLDRpci, MVT::i32, MVT::Other,
+ CPIdx, CurDAG->getEntryNode());
+ else {
+ SDOperand Ops[] = {
+ CPIdx,
+ CurDAG->getRegister(0, MVT::i32),
+ CurDAG->getTargetConstant(0, MVT::i32),
+ CurDAG->getEntryNode()
+ };
+ ResNode = CurDAG->getTargetNode(ARM::LDR, MVT::i32, MVT::Other, Ops, 4);
+ }
ReplaceUses(Op, SDOperand(ResNode, 0));
return NULL;
}
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index fa7afea976..677b6f4133 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -220,10 +220,14 @@ def tLDRSH : TI2<(ops GPR:$dst, t_addrmode_rr:$addr),
"ldrsh $dst, $addr",
[(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
-// def tLDRpci
def tLDRspi : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
"ldr $dst, $addr",
[(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
+
+// Load tconstpool
+def tLDRpci : TIs<(ops GPR:$dst, i32imm:$addr),
+ "ldr $dst, $addr",
+ [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
} // isLoad
let isStore = 1 in {