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| author | Dan Gohman <gohman@apple.com> | 2009-03-13 20:42:20 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-03-13 20:42:20 +0000 |
| commit | 14ea1ec2324cb595f2e035bbf54ddcd483f17c11 (patch) | |
| tree | 32414e0df6b4f5c9c28a4f49ed7e2990bdf511ec /utils/TableGen/TGLexer.cpp | |
| parent | 71503710972ac747e6eaf76877cf1118d2059fce (diff) | |
Fix FastISel's assumption that i1 values are always zero-extended
by inserting explicit zero extensions where necessary. Included
is a testcase where SelectionDAG produces a virtual register
holding an i1 value which FastISel previously mistakenly assumed
to be zero-extended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66941 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/TGLexer.cpp')
0 files changed, 0 insertions, 0 deletions