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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-03-29 18:03:59 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-03-29 18:03:59 +0000 |
| commit | c6a96ff6aeeb77e1007364e5603b72f3ab4cc7bd (patch) | |
| tree | ba7f8bdab2bb94e030d23ad040a3fa6512a71921 /utils/TableGen/RegisterInfoEmitter.cpp | |
| parent | 41e2073f623a08504e2e1e5a9fc5c9f22a03eb83 (diff) | |
Add more constness to CodeGenRegisters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153667 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/RegisterInfoEmitter.cpp')
| -rw-r--r-- | utils/TableGen/RegisterInfoEmitter.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index 2380e23264..f082cfa991 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -306,7 +306,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, if (Reg.getSubRegs().empty()) continue; // getSubRegs() orders by SubRegIndex. We want a topological order. - SetVector<CodeGenRegister*> SR; + SetVector<const CodeGenRegister*> SR; Reg.addSubRegsPreOrder(SR, RegBank); OS << " /* " << Reg.getName() << "_SubRegsSet */ "; for (unsigned j = 0, je = SR.size(); j != je; ++j) @@ -351,7 +351,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, OS << "/* " << Reg->getName() << "_SubRegsSet */ " << SubRegIndex << ", "; // FIXME not very nice to recalculate this - SetVector<CodeGenRegister*> SR; + SetVector<const CodeGenRegister*> SR; Reg->addSubRegsPreOrder(SR, RegBank); SubRegIndex += SR.size() + 1; } else |