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| author | Nate Begeman <natebegeman@mac.com> | 2004-09-28 21:01:45 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2004-09-28 21:01:45 +0000 |
| commit | cdd66b524f62ef6acd6bfa4e586edf8a406c4928 (patch) | |
| tree | cb828c35e8a197955f69fee8c438f5443414cd44 /utils/TableGen/CodeGenTarget.cpp | |
| parent | 5b71d3af35f941585acb50de4909cff20f68680d (diff) | |
Add support for the isLoad and isStore flags, needed by the instruction scheduler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16554 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/CodeGenTarget.cpp')
| -rw-r--r-- | utils/TableGen/CodeGenTarget.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp index ba214051cd..f7225f081d 100644 --- a/utils/TableGen/CodeGenTarget.cpp +++ b/utils/TableGen/CodeGenTarget.cpp @@ -195,6 +195,8 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr) isBranch = R->getValueAsBit("isBranch"); isBarrier = R->getValueAsBit("isBarrier"); isCall = R->getValueAsBit("isCall"); + isLoad = R->getValueAsBit("isLoad"); + isStore = R->getValueAsBit("isStore"); isTwoAddress = R->getValueAsBit("isTwoAddress"); isTerminator = R->getValueAsBit("isTerminator"); hasDelaySlot = R->getValueAsBit("hasDelaySlot"); |