Add support to tablegen for specifying subregister classes on a per register class basis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37572 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 10 insertions, 0 deletions

diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp
index 17cea6f2a6..c3c1ac2271 100644
--- a/utils/TableGen/CodeGenTarget.cpp
+++ b/utils/TableGen/CodeGenTarget.cpp
@@ -199,6 +199,16 @@ CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
     Elements.push_back(Reg);
   }
   
+  std::vector<Record*> SubRegClassList = 
+                        R->getValueAsListOfDefs("SubRegClassList");
+  for (unsigned i = 0, e = SubRegClassList.size(); i != e; ++i) {
+    Record *SubRegClass = SubRegClassList[i];
+    if (!SubRegClass->isSubClassOf("RegisterClass"))
+      throw "Register Class member '" + SubRegClass->getName() +
+            "' does not derive from the RegisterClass class!";
+    SubRegClasses.push_back(SubRegClass);
+  }  
+  
   // Allow targets to override the size in bits of the RegisterClass.
   unsigned Size = R->getValueAsInt("Size");