Change instruction description to split OperandList into OutOperandList and

InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 13 insertions, 1 deletions

diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp
index 2aabe51c51..268711da53 100644
--- a/utils/TableGen/CodeGenTarget.cpp
+++ b/utils/TableGen/CodeGenTarget.cpp
@@ -376,13 +376,25 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
   
   DagInit *DI;
   try {
-    DI = R->getValueAsDag("OperandList");
+    DI = R->getValueAsDag("OutOperandList");
   } catch (...) {
     // Error getting operand list, just ignore it (sparcv9).
     AsmString.clear();
     OperandList.clear();
     return;
   }
+  NumDefs = DI->getNumArgs();
+
+  DagInit *IDI;
+  try {
+    IDI = R->getValueAsDag("InOperandList");
+  } catch (...) {
+    // Error getting operand list, just ignore it (sparcv9).
+    AsmString.clear();
+    OperandList.clear();
+    return;
+  }
+  DI = (DagInit*)(new BinOpInit(BinOpInit::CONCAT, DI, IDI))->Fold();
 
   unsigned MIOperandNo = 0;
   std::set<std::string> OperandNames;