aboutsummaryrefslogtreecommitdiff
path: root/utils/TableGen/CodeGenTarget.cpp
diff options
context:
space:
mode:
authorChris Lattner <sabre@nondot.org>2006-03-24 17:58:06 +0000
committerChris Lattner <sabre@nondot.org>2006-03-24 17:58:06 +0000
commit54e869e18cd3d7c6ea6e2bce668c961b6f46f0ea (patch)
tree6edb3d800a28a8f3da17906ab8403a35c9dc4e53 /utils/TableGen/CodeGenTarget.cpp
parent33e71b69e142b5664b1d0ba89a11641aa56f852e (diff)
Like the comment says, prefer to use the implicit add done by [r+r] addressing
modes than emitting an explicit add and using a base of r0. This implements Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27068 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/CodeGenTarget.cpp')
0 files changed, 0 insertions, 0 deletions