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| author | Andrew Trick <atrick@apple.com> | 2012-10-03 23:06:32 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-10-03 23:06:32 +0000 |
| commit | 13745262a8db98d6c4513ff9934db4be75a8b26c (patch) | |
| tree | 94a2e5f6ae75723c8ef8895bbd96fc264d52821d /utils/TableGen/CodeGenSchedule.h | |
| parent | 2062b1260fa9df3e69e7b4d24a657a0ebb7f8710 (diff) | |
Added instregex support to TableGen subtarget emitter.
This allows the processor-specific machine model to override selected
base opcodes without any fanciness.
e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165180 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/CodeGenSchedule.h')
| -rw-r--r-- | utils/TableGen/CodeGenSchedule.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/utils/TableGen/CodeGenSchedule.h b/utils/TableGen/CodeGenSchedule.h index 211c05c8c6..cc3a10223b 100644 --- a/utils/TableGen/CodeGenSchedule.h +++ b/utils/TableGen/CodeGenSchedule.h @@ -15,6 +15,7 @@ #ifndef CODEGEN_SCHEDULE_H #define CODEGEN_SCHEDULE_H +#include "SetTheory.h" #include "llvm/TableGen/Record.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/ADT/DenseMap.h" @@ -208,6 +209,9 @@ class CodeGenSchedModels { RecordKeeper &Records; const CodeGenTarget &Target; + // Map dag expressions to Instruction lists. + SetTheory Sets; + // List of unique processor models. std::vector<CodeGenProcModel> ProcModels; |