Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 6 insertions, 3 deletions

diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp
index bebf1fd56b..a21a31c2bf 100644
--- a/utils/TableGen/CodeEmitterGen.cpp
+++ b/utils/TableGen/CodeEmitterGen.cpp
@@ -30,7 +30,8 @@ void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
         R->getName() == "DECLARE" ||
         R->getName() == "EXTRACT_SUBREG" ||
         R->getName() == "INSERT_SUBREG" ||
-        R->getName() == "IMPLICIT_DEF") continue;
+        R->getName() == "IMPLICIT_DEF" ||
+        R->getName() == "SUBREG_TO_REG") continue;
     
     BitsInit *BI = R->getValueAsBitsInit("Inst");
 
@@ -105,7 +106,8 @@ void CodeEmitterGen::run(std::ostream &o) {
         R->getName() == "DECLARE" ||
         R->getName() == "EXTRACT_SUBREG" ||
         R->getName() == "INSERT_SUBREG" ||
-        R->getName() == "IMPLICIT_DEF") {
+        R->getName() == "IMPLICIT_DEF" ||
+        R->getName() == "SUBREG_TO_REG") {
       o << "    0U";
       continue;
     }
@@ -139,7 +141,8 @@ void CodeEmitterGen::run(std::ostream &o) {
         InstName == "DECLARE"||
         InstName == "EXTRACT_SUBREG" ||
         InstName == "INSERT_SUBREG" ||
-        InstName == "IMPLICIT_DEF") continue;
+        InstName == "IMPLICIT_DEF" ||
+        InstName == "SUBREG_TO_REG") continue;
     
     BitsInit *BI = R->getValueAsBitsInit("Inst");
     const std::vector<RecordVal> &Vals = R->getValues();