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| author | Jack Carter <jcarter@mips.com> | 2013-01-12 01:03:14 +0000 |
|---|---|---|
| committer | Jack Carter <jcarter@mips.com> | 2013-01-12 01:03:14 +0000 |
| commit | ec3199f675b17b12fd779df557c6bff25aa4e862 (patch) | |
| tree | 78698360753de940b26df9f3832d2c4dbec4adb8 /unittests/IR/AttributesTest.cpp | |
| parent | 6d6132986d2ef14bbf9d76f5acbf2a0bace32d69 (diff) | |
This patch tackles the problem of parsing Mips
register names in the standalone assembler llvm-mc.
Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.
The problem is resolved by the Mips specific AsmParser
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172284 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'unittests/IR/AttributesTest.cpp')
0 files changed, 0 insertions, 0 deletions