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authorNadav Rotem <nrotem@apple.com>2013-01-11 19:54:13 +0000
committerNadav Rotem <nrotem@apple.com>2013-01-11 19:54:13 +0000
commit3e40d927a775994d8f4c2d30695be69c248fa16c (patch)
treedf77a5ea9b62e25f73f4409299efc382d9fdfb72 /test/Transforms/LoopVectorize/ARM/gcc-examples.ll
parent9c0d0f55da1724d303d4b630101b6444b20a4223 (diff)
ARM Cost Model: Modify the target independent cost model to ask
the target if it supports the different CAST types. We didn't do this on X86 because of the different register sizes and types, but on ARM this makes sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172245 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Transforms/LoopVectorize/ARM/gcc-examples.ll')
-rw-r--r--test/Transforms/LoopVectorize/ARM/gcc-examples.ll6
1 files changed, 3 insertions, 3 deletions
diff --git a/test/Transforms/LoopVectorize/ARM/gcc-examples.ll b/test/Transforms/LoopVectorize/ARM/gcc-examples.ll
index 6af4af6ebd..6a68e81bca 100644
--- a/test/Transforms/LoopVectorize/ARM/gcc-examples.ll
+++ b/test/Transforms/LoopVectorize/ARM/gcc-examples.ll
@@ -35,9 +35,9 @@ define void @example1() nounwind uwtable ssp {
}
;CHECK: @example10b
-;CHECK: load <2 x i16>
-;CHECK: sext <2 x i16>
-;CHECK: store <2 x i32>
+;CHECK: load <4 x i16>
+;CHECK: sext <4 x i16>
+;CHECK: store <4 x i32>
;CHECK: ret void
define void @example10b(i16* noalias nocapture %sa, i16* noalias nocapture %sb, i16* noalias nocapture %sc, i32* noalias nocapture %ia, i32* noalias nocapture %ib, i32* noalias nocapture %ic) nounwind uwtable ssp {
br label %1