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authorMichael Liao <michael.liao@intel.com>2013-04-11 04:52:28 +0000
committerMichael Liao <michael.liao@intel.com>2013-04-11 04:52:28 +0000
commit02d2e612521954b5ff7c1ba6fd53e36bc51e1c48 (patch)
treeaf6fc7afc6bc91ff6926a48e7819b9538dc1bf68 /test/MC/X86/x86-64.s
parent959ddbb5e0e088f4d5c3f8c015de3caf0baa6e6c (diff)
Add CLAC/STAC instruction encoding/decoding support
As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/X86/x86-64.s')
-rw-r--r--test/MC/X86/x86-64.s8
1 files changed, 8 insertions, 0 deletions
diff --git a/test/MC/X86/x86-64.s b/test/MC/X86/x86-64.s
index c5f1d15f8f..521a0776d8 100644
--- a/test/MC/X86/x86-64.s
+++ b/test/MC/X86/x86-64.s
@@ -1228,3 +1228,11 @@ sysexitl
// CHECK: sysexitq
// CHECK: encoding: [0x48,0x0f,0x35]
sysexitq
+
+// CHECK: clac
+// CHECK: encoding: [0x0f,0x01,0xca]
+clac
+
+// CHECK: stac
+// CHECK: encoding: [0x0f,0x01,0xcb]
+stac