diff options
| author | Andrew Trick <atrick@apple.com> | 2013-01-09 03:36:49 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2013-01-09 03:36:49 +0000 |
| commit | 47579cf390c42e0577519e0a2b6044baece9df00 (patch) | |
| tree | 2744c5de5c5c825a168a20f90b9e099d8feaaf88 /test/CodeGen | |
| parent | 2af949ddddfaf2feb4a446c754e09d2d8c207ce4 (diff) | |
MIsched: add an ILP window property to machine model.
This was an experimental option, but needs to be defined
per-target. e.g. PPC A2 needs to aggressively hide latency.
I converted some in-order scheduling tests to A2. Hal is working on
more test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/PowerPC/misched-inorder-latency.ll (renamed from test/CodeGen/ARM/misched-inorder-latency.ll) | 33 |
1 files changed, 20 insertions, 13 deletions
diff --git a/test/CodeGen/ARM/misched-inorder-latency.ll b/test/CodeGen/PowerPC/misched-inorder-latency.ll index 8c06b4ce6e..8fae7ad4d1 100644 --- a/test/CodeGen/ARM/misched-inorder-latency.ll +++ b/test/CodeGen/PowerPC/misched-inorder-latency.ll @@ -1,15 +1,15 @@ -; RUN: llc < %s -enable-misched -march=thumb -mcpu=swift \ -; RUN: -pre-RA-sched=source -scheditins=false -ilp-window=0 \ +; RUN: llc < %s -enable-misched -pre-RA-sched=source -scheditins=false \ ; RUN: -disable-ifcvt-triangle-false -disable-post-ra | FileCheck %s ; -; For these tests, we set -ilp-window=0 to simulate in order processor. +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-bgq-linux" -; %val1 is a 3-cycle load live out of %entry. It should be hoisted +; %val1 is a load live out of %entry. It should be hoisted ; above the add. -; CHECK: @testload +; CHECK: testload: ; CHECK: %entry -; CHECK: ldr -; CHECK: adds +; CHECK: lwz +; CHECK: addi ; CHECK: bne ; CHECK: %true define i32 @testload(i32 *%ptr, i32 %sumin) { @@ -34,15 +34,22 @@ end: ; The prefetch gets a default latency of 3 cycles and should be hoisted ; above the add. ; -; CHECK: @testprefetch +; CHECK: testprefetch: ; CHECK: %entry -; CHECK: pld -; CHECK: adds -; CHECK: bx +; CHECK: dcbt +; CHECK: addi +; CHECK: blr define i32 @testprefetch(i8 *%ptr, i32 %i) { entry: - %tmp = add i32 %i, 1 + %val1 = add i32 %i, 1 tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 ) - ret i32 %tmp + %p = icmp eq i32 %i, 0 + br i1 %p, label %true, label %end +true: + %val2 = add i32 %val1, 1 + br label %end +end: + %valmerge = phi i32 [ %val1, %entry], [ %val2, %true ] + ret i32 %valmerge } declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind |