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authorNadav Rotem <nrotem@apple.com>2012-12-28 05:45:24 +0000
committerNadav Rotem <nrotem@apple.com>2012-12-28 05:45:24 +0000
commit0509db27386f5cafffd364618365ecda741cf0bd (patch)
tree2ef5af4e9f96faee5e55a274cbd6aede69de6229 /test/CodeGen/X86
parent587fb1dd30b73afb3c83a1e88d9ea101a0b28ab2 (diff)
AVX: Move the ZEXT/ANYEXT DAGCo optimizations to the lowering of these optimizations. The old test cases still cover all of these lowering/optimizations. The single change that we have is that now anyext does not need to zero a register, because it does not use the exact code path as the zero_extend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171178 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86')
-rwxr-xr-xtest/CodeGen/X86/avx-zext.ll3
1 files changed, 1 insertions, 2 deletions
diff --git a/test/CodeGen/X86/avx-zext.ll b/test/CodeGen/X86/avx-zext.ll
index b630e9d146..582537ea90 100755
--- a/test/CodeGen/X86/avx-zext.ll
+++ b/test/CodeGen/X86/avx-zext.ll
@@ -18,11 +18,10 @@ define <4 x i64> @zext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp
ret <4 x i64>%B
}
-
define <8 x i32> @zext_8i8_to_8i32(<8 x i8> %z) {
;CHECK: zext_8i8_to_8i32
;CHECK: vpunpckhwd
-;CHECK: vpunpcklwd
+;CHECK: vpmovzxwd
;CHECK: vinsertf128
;CHECK: ret
%t = zext <8 x i8> %z to <8 x i32>