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| author | Eric Christopher <echristo@apple.com> | 2011-07-14 20:13:52 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@apple.com> | 2011-07-14 20:13:52 +0000 |
| commit | 5427edeb68d653ced860ed14f83848ebbb01b64b (patch) | |
| tree | b01308b66fc14e73a28e086772afbe5487869674 /test/CodeGen/X86/inline-asm.ll | |
| parent | c83d504085c17697f2a24d0a9fbad4503105ec41 (diff) | |
Check register class matching instead of width of type matching
when determining validity of matching constraint. Allow i1
types access to the GR8 reg class for x86.
Fixes PR10352 and rdar://9777108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135180 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/inline-asm.ll')
| -rw-r--r-- | test/CodeGen/X86/inline-asm.ll | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/test/CodeGen/X86/inline-asm.ll b/test/CodeGen/X86/inline-asm.ll index 603be8aa56..eef6c2f377 100644 --- a/test/CodeGen/X86/inline-asm.ll +++ b/test/CodeGen/X86/inline-asm.ll @@ -30,3 +30,16 @@ entry: %0 = tail call i32 asm "test", "=l,~{dirflag},~{fpsr},~{flags}"() nounwind ret i32 0 } + +; rdar://9777108 PR10352 +define void @test6(i1 zeroext %desired) nounwind { +entry: + tail call void asm sideeffect "foo $0", "q,~{dirflag},~{fpsr},~{flags}"(i1 %desired) nounwind + ret void +} + +define void @test7(i1 zeroext %desired, i32* %p) nounwind { +entry: + %0 = tail call i8 asm sideeffect "xchg $0, $1", "=r,*m,0,~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %p, i1 %desired) nounwind + ret void +} |