Fix a minor bug in two-address pass. It was missing a commute opportunity.

regB = move RCX
regA = op regB, regC
RAX  = move regA
where both regB and regC are killed. If regB is constrainted to non-compatible
physical registers but regC is not constrainted at all, then it's better to
commute the instruction.
       movl    %edi, %eax
       shlq    $32, %rcx
       leaq    (%rcx,%rax), %rax
=>
       movl    %edi, %eax
       shlq    $32, %rcx
       orq     %rcx, %rax
rdar://8762995


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121793 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 43 insertions, 5 deletions

diff --git a/test/CodeGen/X86/commute-two-addr.ll b/test/CodeGen/X86/commute-two-addr.ll
index 56ea26b658..89b436e75c 100644
--- a/test/CodeGen/X86/commute-two-addr.ll
+++ b/test/CodeGen/X86/commute-two-addr.ll
@@ -2,24 +2,62 @@
 ; insertion of register-register copies.
 
 ; Make sure there are only 3 mov's for each testcase
-; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
-; RUN:   grep {\\\<mov\\\>} | count 6
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu   | FileCheck %s -check-prefix=LINUX
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s -check-prefix=DARWIN
 
 
-target triple = "i686-pc-linux-gnu"
 @G = external global i32                ; <i32*> [#uses=2]
 
 declare void @ext(i32)
 
-define i32 @add_test(i32 %X, i32 %Y) {
+define i32 @t1(i32 %X, i32 %Y) nounwind {
+; LINUX: t1:
+; LINUX: movl 4(%esp), %eax
+; LINUX: movl 8(%esp), %ecx
+; LINUX: addl %eax, %ecx
+; LINUX: movl %ecx, G
         %Z = add i32 %X, %Y             ; <i32> [#uses=1]
         store i32 %Z, i32* @G
         ret i32 %X
 }
 
-define i32 @xor_test(i32 %X, i32 %Y) {
+define i32 @t2(i32 %X, i32 %Y) nounwind {
+; LINUX: t2:
+; LINUX: movl 4(%esp), %eax
+; LINUX: movl 8(%esp), %ecx
+; LINUX: xorl %eax, %ecx
+; LINUX: movl %ecx, G
         %Z = xor i32 %X, %Y             ; <i32> [#uses=1]
         store i32 %Z, i32* @G
         ret i32 %X
 }
 
+; rdar://8762995
+%0 = type { i64, i32 }
+
+define %0 @t3(i32 %lb, i8 zeroext %has_lb, i8 zeroext %lb_inclusive, i32 %ub, i8 zeroext %has_ub, i8 zeroext %ub_inclusive) nounwind {
+entry:
+; DARWIN: t3:
+; DARWIN: shlq $32, %rcx
+; DARWIN-NOT: leaq
+; DARWIN: orq %rcx, %rax
+; DARWIN-NOT: mov
+; DARWIN: shll $16
+  %tmp21 = zext i32 %lb to i64
+  %tmp23 = zext i32 %ub to i64
+  %tmp24 = shl i64 %tmp23, 32
+  %ins26 = or i64 %tmp24, %tmp21
+  %tmp28 = zext i8 %has_lb to i32
+  %tmp33 = zext i8 %has_ub to i32
+  %tmp34 = shl i32 %tmp33, 8
+  %tmp38 = zext i8 %lb_inclusive to i32
+  %tmp39 = shl i32 %tmp38, 16
+  %tmp43 = zext i8 %ub_inclusive to i32
+  %tmp44 = shl i32 %tmp43, 24
+  %ins31 = or i32 %tmp39, %tmp28
+  %ins36 = or i32 %ins31, %tmp34
+  %ins46 = or i32 %ins36, %tmp44
+  %tmp16 = insertvalue %0 undef, i64 %ins26, 0
+  %tmp19 = insertvalue %0 %tmp16, i32 %ins46, 1
+  ret %0 %tmp19
+}