diff options
author | Alexander Kornienko <alexfh@google.com> | 2013-03-26 02:28:59 +0000 |
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committer | Alexander Kornienko <alexfh@google.com> | 2013-03-26 02:28:59 +0000 |
commit | d934545ae6a00aa8a8179a93d11cbd93a5240849 (patch) | |
tree | ab44db08aa63a8f94a3e09d6491c4156c624af96 /test/CodeGen/PowerPC/2010-02-12-saveCR.ll | |
parent | 868d4470cdfa9472353ea2a49a6c456ddae9c95b (diff) | |
parent | c204410d6bc435e7cb8ea768759a54135e8e92b5 (diff) |
Updating branches/google/testing to r177703testing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/google/testing@177985 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/2010-02-12-saveCR.ll')
-rw-r--r-- | test/CodeGen/PowerPC/2010-02-12-saveCR.ll | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll index 974a99a52c..0da6e4351b 100644 --- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll +++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll @@ -6,17 +6,17 @@ target triple = "powerpc-apple-darwin9.6" define void @foo() nounwind { entry: -;CHECK: mfcr r2 -;CHECK: lis r3, 1 -;CHECK: rlwinm r2, r2, 8, 0, 31 -;CHECK: ori r3, r3, 34524 -;CHECK: stwx r2, r1, r3 +;CHECK: mfcr r0 +;CHECK: lis r2, 1 +;CHECK: rlwinm r0, r0, 8, 0, 31 +;CHECK: ori r2, r2, 34540 +;CHECK: stwx r0, r1, r2 ; Make sure that the register scavenger returns the same temporary register. -;CHECK: mfcr r2 -;CHECK: lis r3, 1 -;CHECK: rlwinm r2, r2, 12, 0, 31 -;CHECK: ori r3, r3, 34520 -;CHECK: stwx r2, r1, r3 +;CHECK: lis r2, 1 +;CHECK: mfcr r0 +;CHECK: ori r2, r2, 34536 +;CHECK: rlwinm r0, r0, 12, 0, 31 +;CHECK: stwx r0, r1, r2 %x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] %x1 = bitcast [100000 x i8]* %x to i8* ; <i8*> [#uses=1] @@ -25,11 +25,11 @@ entry: br label %return return: ; preds = %entry -;CHECK: lis r3, 1 -;CHECK: ori r3, r3, 34524 -;CHECK: lwzx r2, r1, r3 -;CHECK: rlwinm r2, r2, 24, 0, 31 -;CHECK: mtcrf 32, r2 +;CHECK: lis r2, 1 +;CHECK: ori r2, r2, 34540 +;CHECK: lwzx r0, r1, r2 +;CHECK: rlwinm r0, r0, 24, 0, 31 +;CHECK: mtcrf 32, r0 ret void } |