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| author | Jack Carter <jcarter@mips.com> | 2012-07-02 22:39:45 +0000 |
|---|---|---|
| committer | Jack Carter <jcarter@mips.com> | 2012-07-02 22:39:45 +0000 |
| commit | 1b055ce320fa13f6f1ac81670d11b45e01f79876 (patch) | |
| tree | 0879af89a59a243b917435c0ace1d40940d559d2 /test/CodeGen/Mips/inlineasm-operand-code.ll | |
| parent | 3d4ed0857437c2bbea4dcabc949d180860433d1d (diff) | |
mips32 long long register inline asm constraint support.
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159610 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/inlineasm-operand-code.ll')
| -rw-r--r-- | test/CodeGen/Mips/inlineasm-operand-code.ll | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/inlineasm-operand-code.ll b/test/CodeGen/Mips/inlineasm-operand-code.ll index ca4f3e4c5a..d75f7f2f80 100644 --- a/test/CodeGen/Mips/inlineasm-operand-code.ll +++ b/test/CodeGen/Mips/inlineasm-operand-code.ll @@ -41,5 +41,11 @@ entry: ;CHECK: #NO_APP tail call i32 asm sideeffect "addi $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind +; a long long in 32 bit mode (use to assert) +;CHECK: #APP +;CHECK: addi ${{[0-9]+}},${{[0-9]+}},3 +;CHECK: #NO_APP + tail call i64 asm sideeffect "addi $0,$1,$2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind + ret i32 0 } |