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authorEvan Cheng <evan.cheng@apple.com>2009-03-25 20:20:11 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-03-25 20:20:11 +0000
commit3927f438b5a9fdadc17257802b09430b16d225f9 (patch)
tree143702bdf5385d529554810976ccf03ba8e612fc /test/CodeGen/CellSPU
parenta466ee3106de678c3db38c97c2af21289b403ee7 (diff)
Revert 67132. This is breaking some objective-c apps.
Also fixes SDISel so it *does not* force promote return value if the function is not marked signext / zeroext. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67701 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/CellSPU')
-rw-r--r--test/CodeGen/CellSPU/and_ops.ll4
-rw-r--r--test/CodeGen/CellSPU/eqv.ll3
-rw-r--r--test/CodeGen/CellSPU/nand.ll4
-rw-r--r--test/CodeGen/CellSPU/or_ops.ll1
-rw-r--r--test/CodeGen/CellSPU/shift_ops.ll2
-rw-r--r--test/CodeGen/CellSPU/stores.ll10
-rw-r--r--test/CodeGen/CellSPU/struct_1.ll4
7 files changed, 20 insertions, 8 deletions
diff --git a/test/CodeGen/CellSPU/and_ops.ll b/test/CodeGen/CellSPU/and_ops.ll
index cb066963b1..a18b6f8d05 100644
--- a/test/CodeGen/CellSPU/and_ops.ll
+++ b/test/CodeGen/CellSPU/and_ops.ll
@@ -1,7 +1,7 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
-; RUN: grep and %t1.s | count 230
+; RUN: grep and %t1.s | count 234
; RUN: grep andc %t1.s | count 85
-; RUN: grep andi %t1.s | count 35
+; RUN: grep andi %t1.s | count 37
; RUN: grep andhi %t1.s | count 30
; RUN: grep andbi %t1.s | count 4
diff --git a/test/CodeGen/CellSPU/eqv.ll b/test/CodeGen/CellSPU/eqv.ll
index a578315c6b..5406956772 100644
--- a/test/CodeGen/CellSPU/eqv.ll
+++ b/test/CodeGen/CellSPU/eqv.ll
@@ -1,5 +1,8 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep eqv %t1.s | count 18
+; RUN: grep xshw %t1.s | count 6
+; RUN: grep xsbh %t1.s | count 3
+; RUN: grep andi %t1.s | count 3
; Test the 'eqv' instruction, whose boolean expression is:
; (a & b) | (~a & ~b), which simplifies to
diff --git a/test/CodeGen/CellSPU/nand.ll b/test/CodeGen/CellSPU/nand.ll
index ccbd5d90e5..841a3ec54d 100644
--- a/test/CodeGen/CellSPU/nand.ll
+++ b/test/CodeGen/CellSPU/nand.ll
@@ -1,6 +1,8 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep nand %t1.s | count 90
-; RUN: grep and %t1.s | count 90
+; RUN: grep and %t1.s | count 94
+; RUN: grep xsbh %t1.s | count 2
+; RUN: grep xshw %t1.s | count 4
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu"
diff --git a/test/CodeGen/CellSPU/or_ops.ll b/test/CodeGen/CellSPU/or_ops.ll
index 49e5ec36d2..4e9da8f129 100644
--- a/test/CodeGen/CellSPU/or_ops.ll
+++ b/test/CodeGen/CellSPU/or_ops.ll
@@ -1,4 +1,5 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: grep and %t1.s | count 2
; RUN: grep orc %t1.s | count 85
; RUN: grep ori %t1.s | count 30
; RUN: grep orhi %t1.s | count 30
diff --git a/test/CodeGen/CellSPU/shift_ops.ll b/test/CodeGen/CellSPU/shift_ops.ll
index 3b7dacd3cd..3c26baa7c7 100644
--- a/test/CodeGen/CellSPU/shift_ops.ll
+++ b/test/CodeGen/CellSPU/shift_ops.ll
@@ -3,6 +3,8 @@
; RUN: grep {shlhi } %t1.s | count 3
; RUN: grep {shl } %t1.s | count 9
; RUN: grep {shli } %t1.s | count 3
+; RUN: grep {xshw } %t1.s | count 5
+; RUN: grep {and } %t1.s | count 5
; RUN: grep {andi } %t1.s | count 2
; RUN: grep {rotmi } %t1.s | count 2
; RUN: grep {rotqmbyi } %t1.s | count 1
diff --git a/test/CodeGen/CellSPU/stores.ll b/test/CodeGen/CellSPU/stores.ll
index f59bfd49ac..f2f35ef4db 100644
--- a/test/CodeGen/CellSPU/stores.ll
+++ b/test/CodeGen/CellSPU/stores.ll
@@ -6,13 +6,13 @@
; RUN: grep 771 %t1.s | count 4
; RUN: grep 515 %t1.s | count 2
; RUN: grep 1799 %t1.s | count 2
-; RUN: grep 1543 %t1.s | count 3
-; RUN: grep 1029 %t1.s | count 1
+; RUN: grep 1543 %t1.s | count 5
+; RUN: grep 1029 %t1.s | count 3
; RUN: grep {shli.*, 4} %t1.s | count 4
; RUN: grep stqx %t1.s | count 4
-; RUN: grep ilhu %t1.s | count 9
-; RUN: grep iohl %t1.s | count 6
-; RUN: grep shufb %t1.s | count 13
+; RUN: grep ilhu %t1.s | count 11
+; RUN: grep iohl %t1.s | count 8
+; RUN: grep shufb %t1.s | count 15
; RUN: grep frds %t1.s | count 1
; ModuleID = 'stores.bc'
diff --git a/test/CodeGen/CellSPU/struct_1.ll b/test/CodeGen/CellSPU/struct_1.ll
index 260a7f4198..82d319dd10 100644
--- a/test/CodeGen/CellSPU/struct_1.ll
+++ b/test/CodeGen/CellSPU/struct_1.ll
@@ -3,6 +3,8 @@
; RUN: grep lqa %t1.s | count 5
; RUN: grep lqd %t1.s | count 11
; RUN: grep rotqbyi %t1.s | count 7
+; RUN: grep xshw %t1.s | count 1
+; RUN: grep andi %t1.s | count 5
; RUN: grep cbd %t1.s | count 3
; RUN: grep chd %t1.s | count 1
; RUN: grep cwd %t1.s | count 3
@@ -12,6 +14,8 @@
; RUN: grep ilhu %t2.s | count 16
; RUN: grep lqd %t2.s | count 16
; RUN: grep rotqbyi %t2.s | count 7
+; RUN: grep xshw %t2.s | count 1
+; RUN: grep andi %t2.s | count 5
; RUN: grep cbd %t2.s | count 3
; RUN: grep chd %t2.s | count 1
; RUN: grep cwd %t2.s | count 3