diff options
| author | Chris Lattner <sabre@nondot.org> | 2010-04-15 05:28:43 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-04-15 05:28:43 +0000 |
| commit | efcddc33256512a08d7182783e2262da27f27cdd (patch) | |
| tree | 226d1a8b111b0e4fcf7ca88b4f9e5a81daa135f2 /lib | |
| parent | 2392ae7d7344674dc3d946e324342515f4771b90 (diff) | |
add a simple dag combine to replace trivial shl+lshr with
and. This happens with the store->load narrowing stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101348 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 671c507705..5974aff03c 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -2735,6 +2735,15 @@ SDValue DAGCombiner::visitSRL(SDNode *N) { return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), DAG.getConstant(c1 + c2, N1.getValueType())); } + + // fold (srl (shl x, c), c) -> (and x, cst2) + if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && + N0.getValueSizeInBits() <= 64) { + uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); + return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), + DAG.getConstant(~0ULL >> ShAmt, VT)); + } + // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { |