diff options
| author | Chris Lattner <sabre@nondot.org> | 2006-03-22 01:44:36 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-03-22 01:44:36 +0000 |
| commit | eb8b09f69f0949f7ab7426d9c44ec45acd9dbdaa (patch) | |
| tree | ab746c682d17d4667c0b7a6c97d0e9931b9bdaa9 /lib | |
| parent | 3b9fa89fcaf3eb08397c4c68b60c72fc73f8ab44 (diff) | |
Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26935 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrFormats.td | 2 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 15 |
2 files changed, 8 insertions, 9 deletions
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index be0b262783..868771a167 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -595,8 +595,8 @@ class VAForm_1<bits<6> xo, dag OL, string asmstr, : I<4, OL, asmstr, itin> { bits<5> VD; bits<5> VA; - bits<5> VB; bits<5> VC; + bits<5> VB; let Pattern = pattern; diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 3d0a30d0a8..181f156564 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -948,22 +948,21 @@ def RLDICR : MDForm_1<30, 1, let PPC970_Unit = 5 in { // VALU Operations. // VA-Form instructions. 3-input AltiVec ops. -def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), +def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB), "vmaddfp $vD, $vA, $vC, $vB", VecFP, [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC), VRRC:$vB))]>, Requires<[FPContractions]>; -def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), +def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB), "vnmsubfp $vD, $vA, $vC, $vB", VecFP, - [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, - VRRC:$vC), - VRRC:$vB)))]>, + [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC), + VRRC:$vB)))]>, Requires<[FPContractions]>; -def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC), - "vperm $vD, $vA, $vB, $vC", VecPerm, +def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB), + "vperm $vD, $vA, $vC, $vB", VecPerm, [(set VRRC:$vD, - (PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>; + (PPCvperm (v4f32 VRRC:$vA), VRRC:$vC, VRRC:$vB))]>; // VX-Form instructions. AltiVec arithmetic ops. |