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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-07-20 19:44:51 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-07-20 19:44:51 +0000 |
| commit | e1c29be6f08d0e5657cfa3d430816147698c7479 (patch) | |
| tree | 5e79a5c31e253d57edaeacaf1e4ba19bac4362ef /lib | |
| parent | 6f0414a407793bd03ed807ec30f98cf2946cd68e (diff) | |
Add new AVX instruction vinsertf128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108892 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86InstrFormats.td | 5 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 10 |
2 files changed, 15 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td index d8872bc549..1ff26b7e4a 100644 --- a/lib/Target/X86/X86InstrFormats.td +++ b/lib/Target/X86/X86InstrFormats.td @@ -415,10 +415,15 @@ class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm, // Instructions introduced in AVX (no SSE equivalent forms) // // AVX8I - AVX instructions with T8 and OpSize prefix. +// AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8. class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, OpSize, Requires<[HasAVX]>; +class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm, + list<dag> pattern> + : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, OpSize, + Requires<[HasAVX]>; // AES Instruction Templates: // diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index d0e3b42a39..ef3197b4bb 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -4998,4 +4998,14 @@ def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem>; def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem>; def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem>; +// Insert packed floating-point values +def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst), + (ins VR256:$src1, VR128:$src2, i8imm:$src3), + "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + []>, VEX_4V; +def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst), + (ins VR256:$src1, f128mem:$src2, i8imm:$src3), + "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", + []>, VEX_4V; + } // isAsmParserOnly |