diff options
| author | Jim Grosbach <grosbach@apple.com> | 2010-11-09 17:38:15 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-11-09 17:38:15 +0000 |
| commit | d92354c5742ea72abd3039cda5be37cc757d47d2 (patch) | |
| tree | eb3a5f221517f67daf4f832bfb276cad8173dacb /lib | |
| parent | a9a0dde8720d94f96c4e2888801c04c88cdb05cf (diff) | |
For ARM load/store instructions, encode [reg+reg] with no shifter immediate as
a left shift by zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118587 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMMCCodeEmitter.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp index 7b0bf12bff..bd799f233c 100644 --- a/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -277,6 +277,9 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, // ROR - 11 switch (ShOp) { default: llvm_unreachable("Unknown shift opc!"); + case ARM_AM::no_shift: + assert(ShImm == 0 && "Non-zero shift amount with no shift type!"); + // fall through case ARM_AM::lsl: SBits = 0x0; break; case ARM_AM::lsr: SBits = 0x1; break; case ARM_AM::asr: SBits = 0x2; break; |