diff options
| author | Cameron Zwarich <zwarich@apple.com> | 2011-10-05 23:38:50 +0000 |
|---|---|---|
| committer | Cameron Zwarich <zwarich@apple.com> | 2011-10-05 23:38:50 +0000 |
| commit | d78ebe1e12a9aae01cb11d4d10a3d0600407e5ca (patch) | |
| tree | 00ae7f126fe7d16a9198b6921fef433bbb7e3e47 /lib | |
| parent | 5cbef19a1d9860534a573f446970f5c65758fb66 (diff) | |
Remove a check from ARM shifted operand isel helper methods, which were blocking
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141247 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index eabfdbb095..0626240333 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -519,11 +519,6 @@ bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, return false; } - if (Subtarget->isCortexA9() && !N.hasOneUse()) { - // Compute R +/- (R << N) and reuse it. - return false; - } - // Otherwise this is R +/- [possibly shifted] R. ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add; ARM_AM::ShiftOpc ShOpcVal = @@ -1286,11 +1281,6 @@ bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N, return false; } - if (Subtarget->isCortexA9() && !N.hasOneUse()) { - // Compute R + (R << [1,2,3]) and reuse it. - return false; - } - // Look for (R + R) or (R + (R << [1,2,3])). unsigned ShAmt = 0; Base = N.getOperand(0); |