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authorEvan Cheng <evan.cheng@apple.com>2007-09-27 18:46:06 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-09-27 18:46:06 +0000
commitcd1c00cc6521c265784ffc7a1b5baf4ef64d80bc (patch)
tree9fb4c8916c8283dc0a8c8d7dda89729534b9e488 /lib
parentff37adc0ce9eca648f5cb21b028298ef1c8f5a34 (diff)
Avoid inserting a live register more than once.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42410 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp26
1 files changed, 18 insertions, 8 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 6127ab6381..0b218abd4a 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -25,6 +25,7 @@
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h"
+#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include <climits>
@@ -523,17 +524,22 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
if (LiveRegs.empty())
return false;
+ SmallSet<unsigned, 4> RegAdded;
// If this node would clobber any "live" register, then it's not ready.
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
I != E; ++I) {
if (I->Cost < 0) {
unsigned Reg = I->Reg;
- if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep)
- LRegs.push_back(Reg);
+ if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep) {
+ if (RegAdded.insert(Reg))
+ LRegs.push_back(Reg);
+ }
for (const unsigned *Alias = MRI->getAliasSet(Reg);
*Alias; ++Alias)
- if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep)
- LRegs.push_back(*Alias);
+ if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) {
+ if (RegAdded.insert(*Alias))
+ LRegs.push_back(*Alias);
+ }
}
}
@@ -545,12 +551,16 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
if (!TID.ImplicitDefs)
continue;
for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
- if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU)
- LRegs.push_back(*Reg);
+ if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU) {
+ if (RegAdded.insert(*Reg))
+ LRegs.push_back(*Reg);
+ }
for (const unsigned *Alias = MRI->getAliasSet(*Reg);
*Alias; ++Alias)
- if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU)
- LRegs.push_back(*Alias);
+ if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) {
+ if (RegAdded.insert(*Alias))
+ LRegs.push_back(*Alias);
+ }
}
}
return !LRegs.empty();