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authorJim Grosbach <grosbach@apple.com>2011-07-27 22:34:17 +0000
committerJim Grosbach <grosbach@apple.com>2011-07-27 22:34:17 +0000
commitaddec77b54fd77e99fd01f462a3fb8c3c89066fa (patch)
treee9a8a8719e0fb8aa5a7de9e33df9a3a64fae4e11 /lib
parent5f33d13da41f55e7421eee3bbfa410d07bd7af19 (diff)
ARM assembly parsing and encoding support for USAT and USAT16.
Use range checked immediate operands for instructions. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136285 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/ARM/ARMInstrInfo.td8
1 files changed, 5 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 7e9687a7cf..722fff7d1c 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -2785,7 +2785,7 @@ def SSAT16 : AI<(outs GPR:$Rd), (ins imm1_16:$sat_imm, GPR:$Rn), SatFrm,
let Inst{3-0} = Rn;
}
-def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn, shift_imm:$sh),
+def USAT : AI<(outs GPR:$Rd), (ins imm0_31:$sat_imm, GPR:$Rn, shift_imm:$sh),
SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
bits<4> Rd;
bits<5> sat_imm;
@@ -2800,7 +2800,7 @@ def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn, shift_imm:$sh),
let Inst{3-0} = Rn;
}
-def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
+def USAT16 : AI<(outs GPR:$Rd), (ins imm0_15:$sat_imm, GPR:$a), SatFrm,
NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
[/* For disassembly only; pattern left blank */]> {
bits<4> Rd;
@@ -4364,9 +4364,11 @@ def : InstAlias<"rsc${s}${p} $Rdn, $shift",
(RSCrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p,
cc_out:$s)>, Requires<[IsARM]>;
-// SSAT optional shift operand.
+// SSAT/USAT optional shift operand.
def : InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
(SSAT GPR:$Rd, imm1_32:$sat_imm, GPR:$Rn, 0, pred:$p)>;
+def : InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
+ (USAT GPR:$Rd, imm0_31:$sat_imm, GPR:$Rn, 0, pred:$p)>;
// Extend instruction optional rotate operand.