diff options
| author | David Goodwin <david_goodwin@apple.com> | 2009-10-01 22:19:57 +0000 |
|---|---|---|
| committer | David Goodwin <david_goodwin@apple.com> | 2009-10-01 22:19:57 +0000 |
| commit | 9843a93e830e76f96e9a997b3002624a28ca5aa6 (patch) | |
| tree | faad56e6175ff6097b9b93bf2be6cd89bf3657f7 /lib | |
| parent | e4250396ea254b374436e94f391f1adb9bd94d20 (diff) | |
Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/CodeGen/PostRASchedulerList.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARM.td | 5 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMSubtarget.cpp | 8 |
3 files changed, 9 insertions, 6 deletions
diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index eddc489030..2dafa87cf3 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -54,7 +54,7 @@ STATISTIC(NumStalls, "Number of pipeline stalls"); static cl::opt<bool> EnablePostRAScheduler("post-RA-scheduler", cl::desc("Enable scheduling after register allocation"), - cl::init(false)); + cl::init(false), cl::Hidden); static cl::opt<bool> EnableAntiDepBreaking("break-anti-dependencies", cl::desc("Break post-RA scheduling anti-dependencies"), diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index 8069e2b6a8..8851fbbf24 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -40,9 +40,6 @@ def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON", "Enable NEON instructions">; def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2", "Enable Thumb2 instructions">; -def FeatureNEONFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", - "true", - "Use NEON for single-precision FP">; //===----------------------------------------------------------------------===// // ARM Processors supported. @@ -105,7 +102,7 @@ def : ProcNoItin<"arm1156t2f-s", [ArchV6T2, FeatureThumb2, FeatureVFP2]>; // V7 Processors. def : Processor<"cortex-a8", CortexA8Itineraries, - [ArchV7A, FeatureThumb2, FeatureNEON, FeatureNEONFP]>; + [ArchV7A, FeatureThumb2, FeatureNEON]>; def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>; //===----------------------------------------------------------------------===// diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index 704cf7abfb..cf1ee3f029 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp @@ -21,12 +21,16 @@ using namespace llvm; static cl::opt<bool> ReserveR9("arm-reserve-r9", cl::Hidden, cl::desc("Reserve R9, making it unavailable as GPR")); +static cl::opt<bool> +UseNEONFP("arm-use-neon-fp", + cl::desc("Use NEON for single-precision FP"), + cl::init(false), cl::Hidden); ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb) : ARMArchVersion(V4T) , ARMFPUType(None) - , UseNEONForSinglePrecisionFP(false) + , UseNEONForSinglePrecisionFP(UseNEONFP) , IsThumb(isThumb) , ThumbMode(Thumb1) , PostRAScheduler(false) @@ -97,6 +101,8 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS, // Set CPU specific features. if (CPUString == "cortex-a8") { PostRAScheduler = true; + if (UseNEONFP.getPosition() == 0) + UseNEONForSinglePrecisionFP = true; } } |