Convert TargetRegisterInfo's super-register checking to use a pre-computed hash table just like subregister checking does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68669 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 5 insertions, 3 deletions

diff --git a/lib/Target/TargetRegisterInfo.cpp b/lib/Target/TargetRegisterInfo.cpp
index d9911e9e9a..85ecd3d28a 100644
--- a/lib/Target/TargetRegisterInfo.cpp
+++ b/lib/Target/TargetRegisterInfo.cpp
@@ -23,9 +23,11 @@ using namespace llvm;
 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
                              regclass_iterator RCB, regclass_iterator RCE,
                              int CFSO, int CFDO,
-                             const unsigned* subregs, const unsigned subregsize)
-  : SubregHash(subregs), SubregHashSize(subregsize), Desc(D), NumRegs(NR),
-    RegClassBegin(RCB), RegClassEnd(RCE) {
+			     const unsigned* subregs, const unsigned subregsize,
+			 const unsigned* superregs, const unsigned superregsize)
+  : SubregHash(subregs), SubregHashSize(subregsize),
+    SuperregHash(superregs), SuperregHashSize(superregsize),
+    Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) {
   assert(NumRegs < FirstVirtualRegister &&
          "Target has too many physical registers!");