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authorEric Christopher <echristo@apple.com>2011-07-08 00:04:56 +0000
committerEric Christopher <echristo@apple.com>2011-07-08 00:04:56 +0000
commit77ed1353bfd456efd35c2b6e17115ce624d19e92 (patch)
treeb554de3a2d03d904df62e860a852102cfae179f8 /lib
parent794bf17cbe0bac301ef9e52fb4a0295bfdfe0cab (diff)
Go ahead and emit the barrier on x86-64 even without sse2. The
processor supports it just fine. Fixes PR9675 and rdar://9740801 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134664 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp7
1 files changed, 4 insertions, 3 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 01cea3b0a7..0dfc316760 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -9067,10 +9067,11 @@ SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
DebugLoc dl = Op.getDebugLoc();
- if (!Subtarget->hasSSE2()) {
+ // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
+ // There isn't any reason to disable it if the target processor supports it.
+ if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
SDValue Chain = Op.getOperand(0);
- SDValue Zero = DAG.getConstant(0,
- Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
+ SDValue Zero = DAG.getConstant(0, MVT::i32);
SDValue Ops[] = {
DAG.getRegister(X86::ESP, MVT::i32), // Base
DAG.getTargetConstant(1, MVT::i8), // Scale