diff options
| author | Ruchira Sasanka <sasanka@students.uiuc.edu> | 2001-10-18 22:38:52 +0000 |
|---|---|---|
| committer | Ruchira Sasanka <sasanka@students.uiuc.edu> | 2001-10-18 22:38:52 +0000 |
| commit | 735d6e3ee272e57a794c262abce19d202439b826 (patch) | |
| tree | d6052ac02001271ca00e8ad5d1c9aaa00d873867 /lib | |
| parent | 97b8b4410a43bfef4e09a8db855e671b5013d060 (diff) | |
Added support for condition code loading/stroing in methods cpReg2Reg etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@911 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/SparcV9/SparcV9RegClassInfo.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/SparcV9/SparcV9RegInfo.cpp | 6 |
2 files changed, 8 insertions, 2 deletions
diff --git a/lib/Target/SparcV9/SparcV9RegClassInfo.cpp b/lib/Target/SparcV9/SparcV9RegClassInfo.cpp index ff01f355ed..3ff0779b58 100644 --- a/lib/Target/SparcV9/SparcV9RegClassInfo.cpp +++ b/lib/Target/SparcV9/SparcV9RegClassInfo.cpp @@ -42,7 +42,7 @@ void SparcIntRegClass::colorIGNode(IGNode * Node, bool IsColorUsedArr[]) const LR->setColor( LR->getSuggestedColor() ); return; } - else { // can't allocate the suggested col + else if ( DEBUG_RA ) { // can't allocate the suggested col cerr << " Could NOT allocate the suggested color for LR "; LR->printSet(); cerr << endl; } @@ -192,7 +192,7 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,bool IsColorUsedArr[]) const LR->setColor( LR->getSuggestedColor() ); return; } - else { // can't allocate the suggested col + else if (DEBUG_RA) { // can't allocate the suggested col cerr << " Could NOT allocate the suggested color for LR "; LR->printSet(); cerr << endl; } diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp index 5756dc32fc..60f4203c38 100644 --- a/lib/Target/SparcV9/SparcV9RegInfo.cpp +++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp @@ -621,6 +621,8 @@ MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg, switch( RegType ) { case IntRegType: + case IntCCRegType: + case FloatCCRegType: MI = new MachineInstr(ADD, 3); MI->SetMachineOperand(0, SrcReg, false); MI->SetMachineOperand(1, SparcIntRegOrder::g0, false); @@ -664,6 +666,8 @@ MachineInstr * UltraSparcRegInfo::cpReg2MemMI(const unsigned SrcReg, switch( RegType ) { case IntRegType: + case IntCCRegType: + case FloatCCRegType: MI = new MachineInstr(STX, 3); MI->SetMachineOperand(0, DestPtrReg, false); MI->SetMachineOperand(1, SrcReg, false); @@ -711,6 +715,8 @@ MachineInstr * UltraSparcRegInfo::cpMem2RegMI(const unsigned SrcPtrReg, switch( RegType ) { case IntRegType: + case IntCCRegType: + case FloatCCRegType: MI = new MachineInstr(LDX, 3); MI->SetMachineOperand(0, SrcPtrReg, false); MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed, |