Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106705 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 61 insertions, 30 deletions

diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td
index 5e8c8258c2..c492853adb 100644
--- a/lib/Target/X86/X86InstrFormats.td
+++ b/lib/Target/X86/X86InstrFormats.td
@@ -228,6 +228,18 @@ class SI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
   let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
 }
 
+// SIi8 - SSE 1 & 2 scalar instructions
+class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
+           list<dag> pattern>
+      : Ii8<o, F, outs, ins, asm, pattern> {
+  let Predicates = !if(hasVEXPrefix /* VEX_4V */,
+            !if(!eq(Prefix, 11 /* XD */), [HasAVX, HasSSE2], [HasAVX, HasSSE1]),
+            !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
+
+  // AVX instructions have a 'v' prefix in the mnemonic
+  let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
+}
+
 // PI - SSE 1 & 2 packed instructions
 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
          Domain d>
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 3ea7ca9943..1afda4a218 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -725,42 +725,61 @@ multiclass sse12_cmp_alt<RegisterClass RC, string asm, Domain d,
             [], d>;
 }
 
-// Comparison instructions
-let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
-  def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
-                    (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
-                    "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
+multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
+                            Operand sse_imm_op, string asm> {
+  def rr : SIi8<0xC2, MRMSrcReg,
+                    (outs RC:$dst), (ins RC:$src1, RC:$src, sse_imm_op:$cc),
+                    asm, []>;
   let mayLoad = 1 in
-  def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
-                    (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
-                    "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
+  def rm : SIi8<0xC2, MRMSrcMem,
+                    (outs RC:$dst), (ins RC:$src1, x86memop:$src, sse_imm_op:$cc),
+                    asm, []>;
+}
 
-  def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
-                    (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
-                    "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
+// FIXME: rename instructions to only use the class above
+multiclass sse12_cmp_scalar_alt<RegisterClass RC, X86MemOperand x86memop,
+                            Operand sse_imm_op, string asm> {
+  def rr_alt : SIi8<0xC2, MRMSrcReg,
+                    (outs RC:$dst), (ins RC:$src1, RC:$src, sse_imm_op:$src2),
+                    asm, []>;
   let mayLoad = 1 in
-  def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
-                    (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
-                    "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
+  def rm_alt : SIi8<0xC2, MRMSrcMem,
+                    (outs RC:$dst), (ins RC:$src1, x86memop:$src, sse_imm_op:$src2),
+                    asm, []>;
+}
 
-// Accept explicit immediate argument form instead of comparison code.
-let isAsmParserOnly = 1 in {
-  def CMPSSrr_alt : SSIi8<0xC2, MRMSrcReg,
-                    (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
-                    "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
-  let mayLoad = 1 in
-  def CMPSSrm_alt : SSIi8<0xC2, MRMSrcMem,
-                    (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
-                    "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
+let neverHasSideEffects = 1, isAsmParserOnly = 1 in {
+  defm VCMPSS  : sse12_cmp_scalar<FR32, f32mem, SSECC,
+                    "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
+                    XS, VEX_4V;
+  defm VCMPSD  : sse12_cmp_scalar<FR64, f64mem, SSECC,
+                    "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
+                    XD, VEX_4V;
 
-  def CMPSDrr_alt : SDIi8<0xC2, MRMSrcReg,
-                    (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
-                    "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
-  let mayLoad = 1 in
-  def CMPSDrm_alt : SDIi8<0xC2, MRMSrcMem,
-                    (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
-                    "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
+  // Accept explicit immediate argument form instead of comparison code.
+  let isAsmParserOnly = 1 in {
+    defm VCMPSS  : sse12_cmp_scalar_alt<FR32, f32mem, i8imm,
+                      "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
+                      XS, VEX_4V;
+    defm VCMPSD  : sse12_cmp_scalar_alt<FR64, f32mem, i8imm,
+                      "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
+                      XD, VEX_4V;
+  }
 }
+
+let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
+  defm CMPSS  : sse12_cmp_scalar<FR32, f32mem, SSECC,
+                    "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
+  defm CMPSD  : sse12_cmp_scalar<FR64, f64mem, SSECC,
+                    "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
+
+  // Accept explicit immediate argument form instead of comparison code.
+  let isAsmParserOnly = 1 in {
+    defm CMPSS  : sse12_cmp_scalar_alt<FR32, f32mem, i8imm,
+                      "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}">, XS;
+    defm CMPSD  : sse12_cmp_scalar_alt<FR64, f32mem, i8imm,
+                      "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}">, XD;
+  }
 }
 
 let Defs = [EFLAGS] in {