diff options
| author | Chris Lattner <sabre@nondot.org> | 2010-02-05 21:21:06 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-02-05 21:21:06 +0000 |
| commit | 35e0e84f93152a20ae40ccf13d6d6ea493953a1c (patch) | |
| tree | eaa5204f14eaee473b0c8a0d3801269f89dc8cdf /lib | |
| parent | ff928976f892a63f814a2f5d052213736c242748 (diff) | |
teach X86MCInstLower to lower the MOV32r0 and MOV8r0
pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95433 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/AsmPrinter/X86MCInstLower.cpp | 12 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 8 |
2 files changed, 14 insertions, 6 deletions
diff --git a/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp b/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp index 20bb7951f9..6e0614ad6c 100644 --- a/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp +++ b/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp @@ -374,12 +374,20 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break; case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break; case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break; - case X86::MOV16r0: LowerSubReg32_Op0(OutMI, X86::MOV32r0); break; - case X86::MOV64r0: LowerSubReg32_Op0(OutMI, X86::MOV32r0); break; case X86::SETB_C8r: LowerUnaryToTwoAddr(OutMI, X86::SBB8rr); break; case X86::SETB_C16r: LowerUnaryToTwoAddr(OutMI, X86::SBB16rr); break; case X86::SETB_C32r: LowerUnaryToTwoAddr(OutMI, X86::SBB32rr); break; case X86::SETB_C64r: LowerUnaryToTwoAddr(OutMI, X86::SBB64rr); break; + case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break; + case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break; + case X86::MOV16r0: + LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0 + LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr + break; + case X86::MOV64r0: + LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV64r0 -> MOV32r0 + LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr + break; } } diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 914978e75d..d604c176b1 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -3739,10 +3739,10 @@ let neverHasSideEffects = 1 in { // Alias instructions that map movr0 to xor. // FIXME: remove when we can teach regalloc that xor reg, reg is ok. +// FIXME: Set encoding to pseudo. let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1 in { -def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), - "xor{b}\t$dst, $dst", +def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "", [(set GR8:$dst, 0)]>; // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller @@ -3754,8 +3754,8 @@ def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins), "", [(set GR16:$dst, 0)]>, OpSize; -def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), - "xor{l}\t$dst, $dst", +// FIXME: Set encoding to pseudo. +def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "", [(set GR32:$dst, 0)]>; } |