aboutsummaryrefslogtreecommitdiff
path: root/lib
diff options
context:
space:
mode:
authorDaniel Dunbar <daniel@zuster.org>2009-08-04 04:02:45 +0000
committerDaniel Dunbar <daniel@zuster.org>2009-08-04 04:02:45 +0000
commit214e22396fe86aa20c587d5c7df9ce63bfd4549e (patch)
tree207b168d9836859d7aecda292bd32f8d9cd31a53 /lib
parent2822e174f6e7d728c03c47cf0fcda8a01253107a (diff)
Remove now unused Module argument to createTargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78043 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/CBackend/CBackend.cpp2
-rw-r--r--lib/Target/CBackend/CTargetMachine.h7
-rw-r--r--lib/Target/CppBackend/CPPBackend.cpp2
-rw-r--r--lib/Target/CppBackend/CPPTargetMachine.h6
-rw-r--r--lib/Target/MSIL/MSILWriter.cpp8
5 files changed, 9 insertions, 16 deletions
diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp
index 7a43233cfc..2892826a85 100644
--- a/lib/Target/CBackend/CBackend.cpp
+++ b/lib/Target/CBackend/CBackend.cpp
@@ -51,7 +51,7 @@ using namespace llvm;
extern "C" void LLVMInitializeCBackendTarget() {
// Register the target.
- RegisterTargetMachineDeprecated<CTargetMachine> X(TheCBackendTarget);
+ RegisterTargetMachine<CTargetMachine> X(TheCBackendTarget);
}
namespace {
diff --git a/lib/Target/CBackend/CTargetMachine.h b/lib/Target/CBackend/CTargetMachine.h
index ffd033f198..715bbdaf0c 100644
--- a/lib/Target/CBackend/CTargetMachine.h
+++ b/lib/Target/CBackend/CTargetMachine.h
@@ -20,11 +20,8 @@
namespace llvm {
struct CTargetMachine : public TargetMachine {
- const TargetData DataLayout; // Calculates type size & alignment
-
- CTargetMachine(const Target &T, const Module &M,
- const std::string &FS)
- : TargetMachine(T), DataLayout(&M) {}
+ CTargetMachine(const Target &T, const std::string &TT, const std::string &FS)
+ : TargetMachine(T) {}
virtual bool WantsWholeFile() const { return true; }
virtual bool addPassesToEmitWholeFile(PassManager &PM,
diff --git a/lib/Target/CppBackend/CPPBackend.cpp b/lib/Target/CppBackend/CPPBackend.cpp
index 69d9ee9890..b552e04c4f 100644
--- a/lib/Target/CppBackend/CPPBackend.cpp
+++ b/lib/Target/CppBackend/CPPBackend.cpp
@@ -74,7 +74,7 @@ static cl::opt<std::string> NameToGenerate("cppfor", cl::Optional,
extern "C" void LLVMInitializeCppBackendTarget() {
// Register the target.
- RegisterTargetMachineDeprecated<CPPTargetMachine> X(TheCppBackendTarget);
+ RegisterTargetMachine<CPPTargetMachine> X(TheCppBackendTarget);
}
namespace {
diff --git a/lib/Target/CppBackend/CPPTargetMachine.h b/lib/Target/CppBackend/CPPTargetMachine.h
index c838b389b9..1f74f76b5a 100644
--- a/lib/Target/CppBackend/CPPTargetMachine.h
+++ b/lib/Target/CppBackend/CPPTargetMachine.h
@@ -22,11 +22,9 @@ namespace llvm {
class formatted_raw_ostream;
struct CPPTargetMachine : public TargetMachine {
- const TargetData DataLayout; // Calculates type size & alignment
-
- CPPTargetMachine(const Target &T, const Module &M,
+ CPPTargetMachine(const Target &T, const std::string &TT,
const std::string &FS)
- : TargetMachine(T), DataLayout(&M) {}
+ : TargetMachine(T) {}
virtual bool WantsWholeFile() const { return true; }
virtual bool addPassesToEmitWholeFile(PassManager &PM,
diff --git a/lib/Target/MSIL/MSILWriter.cpp b/lib/Target/MSIL/MSILWriter.cpp
index 873f9b7125..226d146a0e 100644
--- a/lib/Target/MSIL/MSILWriter.cpp
+++ b/lib/Target/MSIL/MSILWriter.cpp
@@ -31,10 +31,8 @@ using namespace llvm;
namespace llvm {
// TargetMachine for the MSIL
struct VISIBILITY_HIDDEN MSILTarget : public TargetMachine {
- const TargetData DataLayout; // Calculates type size & alignment
-
- MSILTarget(const Target &T, const Module &M, const std::string &FS)
- : TargetMachine(T), DataLayout(&M) {}
+ MSILTarget(const Target &T, const std::string &TT, const std::string &FS)
+ : TargetMachine(T) {}
virtual bool WantsWholeFile() const { return true; }
virtual bool addPassesToEmitWholeFile(PassManager &PM,
@@ -48,7 +46,7 @@ namespace llvm {
extern "C" void LLVMInitializeMSILTarget() {
// Register the target.
- RegisterTargetMachineDeprecated<MSILTarget> X(TheMSILTarget);
+ RegisterTargetMachine<MSILTarget> X(TheMSILTarget);
}
bool MSILModule::runOnModule(Module &M) {