diff options
| author | Craig Topper <craig.topper@gmail.com> | 2012-04-15 23:48:57 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-04-15 23:48:57 +0000 |
| commit | 095c528f30a07f5f7819448ec4f144623239eca8 (patch) | |
| tree | 1767b392517ffdc19f7ceda5fd4418823a256c9d /lib | |
| parent | 2cb1e9dc7da53bae7f1530216b297edd25909933 (diff) | |
Spacing fixes and 80 column fixes. Use 0 instead of 0x80 for undef indices in vpermps/vpermd. Hardware only looks at lower 3-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154780 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index d6188892e6..0382f2bb93 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -3984,15 +3984,15 @@ unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) { EVT VT = N->getValueType(0); - assert((VT.is256BitVector() && VT.getVectorNumElements() == 4) && - "Unsupported vector type for VPERMQ/VPERMPD"); - unsigned NumElts = VT.getVectorNumElements(); + assert((VT.is256BitVector() && NumElts == 4) && + "Unsupported vector type for VPERMQ/VPERMPD"); + unsigned Mask = 0; for (unsigned i = 0; i != NumElts; ++i) { int Elt = N->getMaskElt(i); - if (Elt < 0) + if (Elt < 0) continue; Mask |= Elt << (i*2); } @@ -6650,19 +6650,22 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(Op, Subtarget, DAG); if (BlendOp.getNode()) return BlendOp; + if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) { - SmallVector<SDValue,8> permclMask; + SmallVector<SDValue, 8> permclMask; for (unsigned i = 0; i != 8; ++i) { - permclMask.push_back(DAG.getConstant((M[i] >= 0)?M[i]:0x80, MVT::i32)); + permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32)); } return DAG.getNode(VT.isInteger()? X86ISD::VPERMD:X86ISD::VPERMPS, dl, VT, DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, &permclMask[0], 8), V1); - } - if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64)) - return getTargetShuffleNode(VT.isInteger()? X86ISD::VPERMQ : X86ISD::VPERMPD, dl, VT, V1, + + if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64)) { + unsigned Opcode = VT.isInteger() ? X86ISD::VPERMQ : X86ISD::VPERMPD; + return getTargetShuffleNode(Opcode, dl, VT, V1, getShuffleCLImmediate(SVOp), DAG); + } //===--------------------------------------------------------------------===// |