Little patch to turn (shl (add X, 123), 4) -> (add (shl X, 4), 123 << 4)

This triggers in cases of bitfield additions, opening opportunities for
future improvements.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16834 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 3 insertions, 0 deletions

diff --git a/lib/Transforms/Scalar/InstructionCombining.cpp b/lib/Transforms/Scalar/InstructionCombining.cpp
index 767fc9582b..3febd1dd46 100644
--- a/lib/Transforms/Scalar/InstructionCombining.cpp
+++ b/lib/Transforms/Scalar/InstructionCombining.cpp
@@ -2496,6 +2496,9 @@ Instruction *InstCombiner::visitShiftInst(ShiftInst &I) {
 
           switch (Op0BO->getOpcode()) {
           default: isValid = false; break;   // Do not perform transform!
+          case Instruction::Add:
+            isValid = isLeftShift;
+            break;
           case Instruction::Or:
           case Instruction::Xor:
             highBitSet = false;