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author | Dan Gohman <gohman@apple.com> | 2010-02-14 18:51:39 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2010-02-14 18:51:39 +0000 |
commit | 441a38993e89104c424e00c95cce63c7351f4fc3 (patch) | |
tree | e2ff7063c28ef36afa9d957a047c670b03318dc7 /lib/Transforms/Scalar/LoopStrengthReduce.cpp | |
parent | 6020d85c41987b0b7890d91bf66187aac6e8a3a1 (diff) |
Fix whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96179 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Transforms/Scalar/LoopStrengthReduce.cpp')
-rw-r--r-- | lib/Transforms/Scalar/LoopStrengthReduce.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/lib/Transforms/Scalar/LoopStrengthReduce.cpp index 76afe62768..3e037815e7 100644 --- a/lib/Transforms/Scalar/LoopStrengthReduce.cpp +++ b/lib/Transforms/Scalar/LoopStrengthReduce.cpp @@ -1995,7 +1995,7 @@ void LSRInstance::GenerateReassociations(LSRUse &LU, unsigned LUIdx, /// GenerateCombinations - Generate a formula consisting of all of the /// loop-dominating registers added into a single register. void LSRInstance::GenerateCombinations(LSRUse &LU, unsigned LUIdx, - Formula Base) { + Formula Base) { // This method is only intersting on a plurality of registers. if (Base.BaseRegs.size() <= 1) return; |