diff options
| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-02 05:43:46 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-02 05:43:46 +0000 |
| commit | fa226bccaa90c520cac154df74069bbabb976eab (patch) | |
| tree | 9354e2526b44ac981889e85e45a356a9e535b8eb /lib/Target | |
| parent | ac925653847294a7076060e3dcd4d491e83c711a (diff) | |
Use TRI::has{Sub,Super}ClassEq() where possible.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132455 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/ARM/Thumb1RegisterInfo.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/Blackfin/BlackfinInstrInfo.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.cpp | 3 |
4 files changed, 5 insertions, 6 deletions
diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp index 33cefb6e79..6bf565068e 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -49,7 +49,7 @@ Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii, const TargetRegisterClass* Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const { - if (RC == ARM::tGPRRegisterClass || RC->hasSuperClass(ARM::tGPRRegisterClass)) + if (ARM::tGPRRegClass.hasSubClassEq(RC)) return ARM::tGPRRegisterClass; return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC); } diff --git a/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp b/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp index 9df2aeeecb..42659aed5d 100644 --- a/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp +++ b/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp @@ -117,11 +117,11 @@ bool BlackfinDAGToDAGISel::SelectADDRspii(SDValue Addr, } static inline bool isCC(const TargetRegisterClass *RC) { - return RC == &BF::AnyCCRegClass || BF::AnyCCRegClass.hasSubClass(RC); + return BF::AnyCCRegClass.hasSubClassEq(RC); } static inline bool isDCC(const TargetRegisterClass *RC) { - return RC == &BF::DRegClass || BF::DRegClass.hasSubClass(RC) || isCC(RC); + return BF::DRegClass.hasSubClassEq(RC) || isCC(RC); } static void UpdateNodeOperand(SelectionDAG &DAG, diff --git a/lib/Target/Blackfin/BlackfinInstrInfo.cpp b/lib/Target/Blackfin/BlackfinInstrInfo.cpp index e50d57a31b..598cf2a68c 100644 --- a/lib/Target/Blackfin/BlackfinInstrInfo.cpp +++ b/lib/Target/Blackfin/BlackfinInstrInfo.cpp @@ -160,7 +160,7 @@ static bool inClass(const TargetRegisterClass &Test, if (TargetRegisterInfo::isPhysicalRegister(Reg)) return Test.contains(Reg); else - return &Test==RC || Test.hasSubClass(RC); + return Test.hasSubClassEq(RC); } void diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 68cc2cf3bf..6f67101e7e 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -261,8 +261,7 @@ X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, } break; case X86::sub_8bit_hi: - if (B == &X86::GR8_ABCD_HRegClass || - B->hasSubClass(&X86::GR8_ABCD_HRegClass)) + if (B->hasSubClassEq(&X86::GR8_ABCD_HRegClass)) switch (A->getSize()) { case 2: return getCommonSubClass(A, &X86::GR16_ABCDRegClass); case 4: return getCommonSubClass(A, &X86::GR32_ABCDRegClass); |