diff options
| author | Hal Finkel <hfinkel@anl.gov> | 2012-06-08 15:38:23 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2012-06-08 15:38:23 +0000 |
| commit | daa03ec60475a641bcc66799764977f79997ca45 (patch) | |
| tree | 88764859180b5f2af3a95fd201eaddeba589fa61 /lib/Target | |
| parent | 99f823f94374917174f96a7689955b8463db6816 (diff) | |
Fix a bug in the new PPC CTR-Loops pass.
The code which tests for an induction operation cannot assume that any
ADDI instruction will have a register operand because the operand could
also be a frame index; for example:
%vreg16<def> = ADDI8 <fi#0>, 0; G8RC:%vreg16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158205 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/PowerPC/PPCCTRLoops.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCCTRLoops.cpp b/lib/Target/PowerPC/PPCCTRLoops.cpp index 4671893c3e..5234da71a8 100644 --- a/lib/Target/PowerPC/PPCCTRLoops.cpp +++ b/lib/Target/PowerPC/PPCCTRLoops.cpp @@ -371,6 +371,7 @@ bool PPCCTRLoops::isInductionOperation(const MachineInstr *MI, unsigned IVReg) const { return ((MI->getOpcode() == PPC::ADDI || MI->getOpcode() == PPC::ADDI8) && + MI->getOperand(1).isReg() && // could be a frame index instead MI->getOperand(1).getReg() == IVReg); } |