diff options
author | Vincent Lejeune <vljn@ovi.com> | 2013-04-30 00:14:00 +0000 |
---|---|---|
committer | Vincent Lejeune <vljn@ovi.com> | 2013-04-30 00:14:00 +0000 |
commit | 7097b1ddeab32b72edaf9e0177360b0576b7ecaf (patch) | |
tree | d063d0b0667689e91b8a0fe8a9b2dfd2efd37ff9 /lib/Target | |
parent | b6379de427c009284d47c5fc764f11bbd2bf2484 (diff) |
R600: Take inner dependency into tex/vtx clauses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180757 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/R600/R600ControlFlowFinalizer.cpp | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/lib/Target/R600/R600ControlFlowFinalizer.cpp b/lib/Target/R600/R600ControlFlowFinalizer.cpp index 611d61ace0..e637641e68 100644 --- a/lib/Target/R600/R600ControlFlowFinalizer.cpp +++ b/lib/Target/R600/R600ControlFlowFinalizer.cpp @@ -48,6 +48,7 @@ private: static char ID; const R600InstrInfo *TII; + const R600RegisterInfo &TRI; unsigned MaxFetchInst; const AMDGPUSubtarget &ST; @@ -107,6 +108,35 @@ private: return TII->get(Opcode); } + bool isCompatibleWithClause(const MachineInstr *MI, + std::set<unsigned> &DstRegs, std::set<unsigned> &SrcRegs) const { + unsigned DstMI, SrcMI; + for (MachineInstr::const_mop_iterator I = MI->operands_begin(), + E = MI->operands_end(); I != E; ++I) { + const MachineOperand &MO = *I; + if (!MO.isReg()) + continue; + if (MO.isDef()) + DstMI = MO.getReg(); + if (MO.isUse()) { + unsigned Reg = MO.getReg(); + if (AMDGPU::R600_Reg128RegClass.contains(Reg)) + SrcMI = Reg; + else + SrcMI = TRI.getMatchingSuperReg(Reg, + TRI.getSubRegFromChannel(TRI.getHWRegChan(Reg)), + &AMDGPU::R600_Reg128RegClass); + } + } + if ((DstRegs.find(SrcMI) == DstRegs.end()) && + (SrcRegs.find(DstMI) == SrcRegs.end())) { + SrcRegs.insert(SrcMI); + DstRegs.insert(DstMI); + return true; + } else + return false; + } + ClauseFile MakeFetchClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I) const { @@ -114,6 +144,7 @@ private: std::vector<MachineInstr *> ClauseContent; unsigned AluInstCount = 0; bool IsTex = TII->usesTextureCache(ClauseHead); + std::set<unsigned> DstRegs, SrcRegs; for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) { if (IsTrivialInst(I)) continue; @@ -122,6 +153,8 @@ private: if ((IsTex && !TII->usesTextureCache(I)) || (!IsTex && !TII->usesVertexCache(I))) break; + if (!isCompatibleWithClause(I, DstRegs, SrcRegs)) + break; AluInstCount ++; ClauseContent.push_back(I); } @@ -176,6 +209,7 @@ private: public: R600ControlFlowFinalizer(TargetMachine &tm) : MachineFunctionPass(ID), TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())), + TRI(TII->getRegisterInfo()), ST(tm.getSubtarget<AMDGPUSubtarget>()) { const AMDGPUSubtarget &ST = tm.getSubtarget<AMDGPUSubtarget>(); if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD4XXX) |