diff options
| author | Dale Johannesen <dalej@apple.com> | 2009-02-13 02:29:03 +0000 |
|---|---|---|
| committer | Dale Johannesen <dalej@apple.com> | 2009-02-13 02:29:03 +0000 |
| commit | bd9ef18f74a361e0ed630d373677c6fc0ce3cad9 (patch) | |
| tree | 29e771c0c09825f0e809b36a222fd6092ed52337 /lib/Target/XCore/XCoreInstrInfo.cpp | |
| parent | 536a2f1f8467a17f6d145bd83f25faae1f689839 (diff) | |
Remove refs to non-DebugLoc version of BuildMI from XCore, PIC16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64432 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/XCoreInstrInfo.cpp')
| -rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.cpp | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index 4328411024..e328b460f0 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -302,6 +302,8 @@ unsigned XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond)const{ + // FIXME there should probably be a DebugLoc argument here + DebugLoc dl = DebugLoc::getUnknownLoc(); // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && @@ -310,11 +312,11 @@ XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, if (FBB == 0) { // One way branch. if (Cond.empty()) { // Unconditional branch - BuildMI(&MBB, get(XCore::BRFU_lu6)).addMBB(TBB); + BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(TBB); } else { // Conditional branch. unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); - BuildMI(&MBB, get(Opc)).addReg(Cond[1].getReg()) + BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg()) .addMBB(TBB); } return 1; @@ -323,9 +325,9 @@ XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, // Two-way Conditional branch. assert(Cond.size() == 2 && "Unexpected number of components!"); unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); - BuildMI(&MBB, get(Opc)).addReg(Cond[1].getReg()) + BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg()) .addMBB(TBB); - BuildMI(&MBB, get(XCore::BRFU_lu6)).addMBB(FBB); + BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(FBB); return 2; } |