diff options
| author | Chris Lattner <sabre@nondot.org> | 2009-09-02 05:53:04 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2009-09-02 05:53:04 +0000 |
| commit | 700841617a9cfdc08323449ab14f42513c106430 (patch) | |
| tree | 3d773e649c04ab3273b5dc44944ec9db9c7952f5 /lib/Target/X86/X86Subtarget.cpp | |
| parent | f19f9347b85279100f7d549154e37b6d726c3c94 (diff) | |
Add support for modeling whether or not the processor has support for
conditional moves as a subtarget feature. This is the easy part of
PR4841.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80763 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86Subtarget.cpp')
| -rw-r--r-- | lib/Target/X86/X86Subtarget.cpp | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp index 730872819e..0a015ee7e5 100644 --- a/lib/Target/X86/X86Subtarget.cpp +++ b/lib/Target/X86/X86Subtarget.cpp @@ -235,13 +235,14 @@ void X86Subtarget::AutoDetectSubtargetFeatures() { X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); - if ((EDX >> 23) & 0x1) X86SSELevel = MMX; - if ((EDX >> 25) & 0x1) X86SSELevel = SSE1; - if ((EDX >> 26) & 0x1) X86SSELevel = SSE2; + if ((EDX >> 15) & 1) HasCMov = true; + if ((EDX >> 23) & 1) X86SSELevel = MMX; + if ((EDX >> 25) & 1) X86SSELevel = SSE1; + if ((EDX >> 26) & 1) X86SSELevel = SSE2; if (ECX & 0x1) X86SSELevel = SSE3; - if ((ECX >> 9) & 0x1) X86SSELevel = SSSE3; - if ((ECX >> 19) & 0x1) X86SSELevel = SSE41; - if ((ECX >> 20) & 0x1) X86SSELevel = SSE42; + if ((ECX >> 9) & 1) X86SSELevel = SSSE3; + if ((ECX >> 19) & 1) X86SSELevel = SSE41; + if ((ECX >> 20) & 1) X86SSELevel = SSE42; bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0; bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0; @@ -380,6 +381,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &FS, : PICStyle(PICStyles::None) , X86SSELevel(NoMMXSSE) , X863DNowLevel(NoThreeDNow) + , HasCMov(false) , HasX86_64(false) , HasSSE4A(false) , HasAVX(false) |