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authorAnitha Boyapati <anitha.boyapati@gmail.com>2012-08-16 04:04:02 +0000
committerAnitha Boyapati <anitha.boyapati@gmail.com>2012-08-16 04:04:02 +0000
commit9418f176526623000f817c1dd696b14da3a471e9 (patch)
tree04ab5ce46cfd70fc25eb1014c8dc8742306980c0 /lib/Target/X86/X86.td
parent2e7a01cb42abffa570a72976ab911de255e6384e (diff)
Patch to enable FMA on bdver2 target. Make XOP feature enable FMA4 as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162012 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86.td')
-rw-r--r--lib/Target/X86/X86.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td
index d1574ececd..18e6b7c3d9 100644
--- a/lib/Target/X86/X86.td
+++ b/lib/Target/X86/X86.td
@@ -97,7 +97,7 @@ def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
[FeatureAVX, FeatureSSE4A]>;
def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
"Enable XOP instructions",
- [FeatureAVX, FeatureSSE4A]>;
+ [FeatureFMA4]>;
def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
"HasVectorUAMem", "true",
"Allow unaligned memory operands on vector/SIMD instructions">;
@@ -226,7 +226,7 @@ def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
FeatureAES, FeaturePCLMUL,
FeatureF16C, FeatureLZCNT,
- FeaturePOPCNT, FeatureBMI]>;
+ FeaturePOPCNT, FeatureBMI, FeatureFMA]>;
def : Proc<"winchip-c6", [FeatureMMX]>;
def : Proc<"winchip2", [Feature3DNow]>;