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| author | Preston Gurd <preston.gurd@intel.com> | 2013-03-27 19:14:02 +0000 |
|---|---|---|
| committer | Preston Gurd <preston.gurd@intel.com> | 2013-03-27 19:14:02 +0000 |
| commit | 1edadea42f6f5c393b4fdb9d7ce1cf7eb9c24ab4 (patch) | |
| tree | 0703e20d41246fa36a72779d0d1ba5b58b6ee2d7 /lib/Target/X86/X86.td | |
| parent | e915047fed99221afb8c540d8a7e81038a6483f1 (diff) | |
For the current Atom processor, the fastest way to handle a call
indirect through a memory address is to load the memory address into
a register and then call indirect through the register.
This patch implements this improvement by modifying SelectionDAG to
force a function address which is a memory reference to be loaded
into a virtual register.
Patch by Sriram Murali.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178171 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86.td')
| -rw-r--r-- | lib/Target/X86/X86.td | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td index e87da56cc6..bf095017f8 100644 --- a/lib/Target/X86/X86.td +++ b/lib/Target/X86/X86.td @@ -134,6 +134,9 @@ def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb", def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions", "PadShortFunctions", "true", "Pad short functions">; +def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect", + "CallRegIndirect", "true", + "Call register indirect">; //===----------------------------------------------------------------------===// // X86 processors supported. @@ -181,7 +184,9 @@ def : ProcessorModel<"penryn", SandyBridgeModel, def : ProcessorModel<"atom", AtomModel, [ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B, FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP, - FeatureSlowDivide, FeaturePadShortFunctions]>; + FeatureSlowDivide, + FeatureCallRegIndirect, + FeaturePadShortFunctions]>; // "Arrandale" along with corei3 and corei5 def : ProcessorModel<"corei7", SandyBridgeModel, |