Added support for X86 instruction prefixes so llvm-mc can assemble them. The

Lock prefix, Repeat string operation prefixes and the Segment override prefixes.
Also added versions of the move string and store string instructions without the
repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of
move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is
happy building the disassembler files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95252 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 12 insertions, 2 deletions

diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 3a8f5d5565..b5e5f8b137 100644
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -462,8 +462,18 @@ ParseInstruction(const StringRef &Name, SMLoc NameLoc,
   if (Name.startswith("sal")) {
     std::string Tmp = "shl" + Name.substr(3).str();
     Operands.push_back(X86Operand::CreateToken(Tmp, NameLoc));
-  } else
-    Operands.push_back(X86Operand::CreateToken(Name, NameLoc));
+  } else {
+    // FIXME: This is a hack.  We eventually want to add a general pattern
+    // mechanism to be used in the table gen file for these assembly names that
+    // use the same opcodes.  Also we should only allow the "alternate names"
+    // for rep and repne with the instructions they can only appear with.
+    StringRef PatchedName = Name;
+    if (Name == "repe" || Name == "repz")
+      PatchedName = "rep";
+    else if (Name == "repnz")
+      PatchedName = "repne";
+    Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
+  }
 
   if (getLexer().isNot(AsmToken::EndOfStatement)) {