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authorEvan Cheng <evan.cheng@apple.com>2005-12-10 00:48:20 +0000
committerEvan Cheng <evan.cheng@apple.com>2005-12-10 00:48:20 +0000
commitb51a059b2c47b91a66230ce53410303bacb79a69 (patch)
treef389ac8503f59076ecced0aeeb78fda86b03b722 /lib/Target/TargetSelectionDAG.td
parent7038daf34272d58da160989dd97f0bce39f5b0b1 (diff)
* Added X86 store patterns.
* Added X86 dec patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24654 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/TargetSelectionDAG.td')
-rw-r--r--lib/Target/TargetSelectionDAG.td5
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td
index e0585b756e..193a5c3e0b 100644
--- a/lib/Target/TargetSelectionDAG.td
+++ b/lib/Target/TargetSelectionDAG.td
@@ -137,6 +137,10 @@ def SDTLoad : SDTypeProfile<1, 1, [ // load
SDTCisPtrTy<1>
]>;
+def SDTStore : SDTypeProfile<0, 2, [ // store
+ SDTCisInt<1>
+]>;
+
//===----------------------------------------------------------------------===//
// Selection DAG Node Properties.
//
@@ -227,6 +231,7 @@ def ret : SDNode<"ISD::RET" , SDTRet, [SDNPHasChain]>;
def writeport : SDNode<"ISD::WRITEPORT" , SDTWritePort, [SDNPHasChain]>;
def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
+def store : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>;
//===----------------------------------------------------------------------===//
// Selection DAG Condition Codes